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Imperas and Industry Articles

How much do we pay for a system to be programmable? It depends upon who you ask.

Semiconductor Engineering

 

Programmability has fueled the growth of most semiconductor products, but how much does it actually cost? And is that cost worth it?
The answer is more complicated than a simple efficiency formula. It can vary by application, by maturity of technology in a particular market, and in the context of much larger systems. What’s considered…

Is there room for an even smaller version of a RISC-V processor that could replace 8-bit microcontrollers?

Semiconductor Engineering

 

Microcontrollers exist in almost everything, but can RISC-V satisfy the needs of this market? Is it small enough to replace 8-bit processors? What might help people migrate to a more modern processor architecture?
RISC-V defines a 32-bit processor instruction set architecture (ISA) that is open…

 

To read the full …

As we look back over 2021, there have certainly been some surprises, but the industry continues to take everything in its stride.

Semiconductor Engineering

 

Early in the year, everyone expected that the availability of COVID vaccines would signal the start of a return to normal, but that has certainly not been the case. Now the industry is taking a longer-term view about how to transform business, what is necessary for people to maintain…

Cache coherency is expensive and provides little or negative benefit for some tasks. So why is it still used so frequently?

Semiconductor Engineering

 

Cache coherency, a common technique for improving performance in chips, is becoming less useful as general-purpose processors are supplemented with, and sometimes supplanted by, highly specialized accelerators and other processing elements.
While cache coherency won’t disappear anytime…

The RISC-V market is ripe for domain specific designs.

 

Codasip article on Semiconductor Engineering

 

We weren’t sure what to expect from our first major attendance at a #RISCVSummit. Although we were a founding member of RISC-V – as we’ve been saying quite a lot recently – we have been hiding our light under a bushel…

To read the full article by Rupert Baines, published by Semiconductor Engineering…

Interview with Sanjay Gangal following the announcement of ImperasDV for RISC-V processor verification at the co-located DAC and RISC-V Summit 2021.

EDACafe

The open ISA of RISC-V is generating a lot of interest on the new design freedoms for processor hardware, in this interview Sanjay explores the implications for software development and the growing demand for processor verification solutions. Highlighting the recent announcements on ImperasDV, the latest…

With its new ImperasDV solution, the company aims at enabling all RISC-V developers to accomplish the complex task of processor IP verification more efficiently.

EDACafe

“The greatest migration in verification responsibility in the history of EDA,” from processor IP vendors to SoC designers: this, according to Imperas Software, is the challenge facing SoC development teams as they take advantage from RISC-V customization capabilities…

Embedded Computing Design

RISC-V is known as an open-standard instruction set architecture (ISA) whose base instructions have been frozen to minimize complexity. But more recently it has added a wide range of custom extensions and enhancements that are making it increasingly popular amongst SoC designers building application-specific systems.
The custom functionality adopted in these architectures is often enhanced…

The application of old techniques to new problems only gets you so far. To remove limitations in AI processors, new thinking is required.

Semiconductor Engineering

 

Software and hardware both place limits on how fast an application can run, but finding and eliminating the limitations is becoming more important in this age of multicore heterogeneous processing.
The problem is certainly not new. Gene Amdahl (1922-2015) recognized the issue and published a paper about…