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EDACafe 2021 Interview with Larry Lapides, VP, Imperas Software

Interview with Sanjay Gangal following the announcement of ImperasDV for RISC-V processor verification at the co-located DAC and RISC-V Summit 2021.


The open ISA of RISC-V is generating a lot of interest on the new design freedoms for processor hardware, in this interview Sanjay explores the implications for software development and the growing demand for processor verification solutions. Highlighting the recent announcements on ImperasDV, the latest approach to RISC-V verification based on industry standards and SoC methodologies, plus the latest news with Codasip, the latest RISC-V ratified specifications for 2021, and MIPS selecting Imperas for DV as they transition to the open standard ISA of RISC-V…


To see the full EDACafe video interview with Sanjay Gangal, click here.