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Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

The High But Often Unnecessary Cost Of Coherence

Cache coherency is expensive and provides little or negative benefit for some tasks. So why is it still used so frequently?

Semiconductor Engineering

 

Cache coherency, a common technique for improving performance in chips, is becoming less useful as general-purpose processors are supplemented with, and sometimes supplanted by, highly specialized accelerators and other processing elements.
While cache coherency won’t disappear anytime soon, it is increasingly being viewed as a luxury necessary to preserve a long-standing programming paradigm. As a result, architectures are beginning to limit its use whenever it makes sense…

 

To read the full Semiconductor Engineering article by Brian Bailey, click here.


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Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

ARM TrustZone Platform Modeling Application Note

RISC-V Custom Instruction Flow Application Note

RISC-V Processor Verification: ImperasDV with Synopsys VCS and Verdi Application Note

Comments

  • Shuzo Tanaka, Vice President

    eSOL TRINITY

    Virtual platforms are moving into the mainstream of embedded software flows.  Imperas tools and models lead the market, and adding distribution to our relationship enables us to provide complete and comprehensive solutions to our customers.

  • Dr. Charlie Su, CTO and EVP

    Andes Technology

    All Andes RISC-V CPU cores are extensible. ACE empowers SoC designers to easily add custom instructions on top of our highly efficient cores to fulfill domain-specific acceleration and bring their SoC performance to the next level.

    Our RISC-V CPU cores are supported by the Imperas simulators already. We are excited to extend our cooperation to enable ACE users to use the Imperas fast simulators so that software engineers can also be engaged with the full development cycle and from the early stage.