Verification and debug of AI is a multi-level problem with several stakeholders, each with different tools and responsibilities.

When an AI algorithm is deployed in the field and gives an unexpected result, it’s often not clear whether that result is correct.
So what happened? Was it wrong? And if so, what caused the error? These are often not simple questions to answer. Moreover, as with all verification problems, the only way…

The C-Suite wants the chip industry to use PLM, but are their issues different enough that a more specialized black-box approach would be better?

Product lifecycle management (PLM) and the semiconductor industry have always been separate, but pressure is growing to integrate them. Automotive, IIoT, medical, and other industries see that as the only way to manage many aspects of their business, and as it stands,…

Software and hardware interdependencies complicate debug in embedded designs. New approaches are maturing to help reduce debug time.

Debugging embedded designs is becoming increasingly difficult as the number of observed and possible interactions between hardware and software continue to grow, and as more features are crammed into chips, packages, and systems. But there also appear to be some advances on this front, involving a mix of techniques, including…

Abstraction is the key to custom processor design and verification, but defining the right language and tool flow is a work in progress.

High-quality RISC-V implementations are becoming more numerous, but it is the extensibility of the architecture that is driving a lot of design activity. The challenge is designing and implementing custom processors without having to re-implement them every time at the register transfer level (RTL…

Technologies must evolve to keep up with changing demands, and emulation is no exception.

Emulation is now the cornerstone of verification for advanced chip designs, but how emulation will evolve to meet future demands involving increasingly dense, complex, and heterogeneous architectures isn’t entirely clear.
EDA companies have been investing heavily in emulation, increasing capacity, boosting performance, and adding new…

The cloud cements its role in embedded hardware design.

In the summer of 2018, professors John Hennessy and David Patterson declared a glorious future for custom hardware. The pair had picked up the Association for Computing Machinery’s Turing Award for 2017 for their roles in the development of the reduced instruction set computer (RISC) architectural style in the 1980s. 
Towards the end of their acceptance speech, Patterson pointed to the…

Automatic mapping of software onto existing hardware, or using software to drive hardware design, are highly desired but very difficult.

For the past 20 years, the industry has sought to deploy hardware/software co-design concepts. While it is making progress, software/hardware co-design appears to have a much brighter future. In order to understand the distinction between the two approaches, it is important to define some…

The open ISA of RISC-V means any SoC developer can now design a custom processor - moving the verification task from a few specialist suppliers to all SoC developers. This article looks at the industrial-grade verification and open methodology as used by the OpenHW verification working group.

One of the appealing things about open-source is that it invites…

New approaches emerge as demand for improved power and performance overwhelm design tools.

The semiconductor ecosystem is at a turning point for how to best architect the CPU based on the explosion of data, the increased usage of AI, and the need for differentiation and customization in leading-edge applications.

In the past, much of this would have been accomplished by moving to the next process node. But with the benefits from…