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Imperas and Industry Articles

Reliability concerns throughout a device’s lifetime are driving fundamental changes in where and when these functions occur.

Semiconductor Engineering


While the disciplines of functional verification and test serve different purposes, their histories were once closely intertwined. Recent safety and security monitoring requirements coupled with capabilities being embedded into devices is bringing them closer together again, but can they successfully cooperate…

Developing these systems is just part of the challenge. Making sure they only do what they’re supposed to do may be even harder.

Semiconductor Engineering


New techniques and approaches are starting to be applied to AI and machine learning to ensure they function within acceptable parameters, only doing what they’re supposed to do.
Getting AI/ML/DL systems to work has been one of the biggest leaps in technology in recent years, but understanding how to control and optimize…

A collaboration to verify the Open Source CV32E40P (PULP RI5CY) core using industrial grade techniques provides a set of guidelines for the community.

The Lost Art of Processor Verification


Modern SoC verification has matured to the point that some are suggesting the use of the word ‘prototype’ when referring to the first silicon samples is now unnecessary. This is due in part to the commercial EDA industry, which has provided the innovation and tools used…

Imperas examples of RISC-V Custom Instructions featuring the ChaCha20 stream cipher are used to illustrate the flexibility of the open standard ISA of RISC-V.

Elektor Magazine


The electronics industry seems to have gone crazy for RISC-V. But why? What is RISC-V and how can you participate in it? If you’ve read anything in passing, you’ll know it is a type of processor, and there are some chips available that use it. You may also know that it is "free and open," which primarily accounts for…

What does open-source verification mean in the context of a RISC-V processor core? Does it provide free tools, free testbenches, or the freedom to innovate?

Semiconductor Engineering


Experts at the Table: Semiconductor Engineering sat down to discuss what open source verification means today and what it should evolve into, with Jean-Marie Brunet, senior director for the Emulation Division at Siemens EDA; Ashish Darbari, CEO of…

How RISC-V verification ecosystems support flexibility in approaching a custom processor design.

Semiconductor Engineering


This article is derived from a talk at the RISC-V Summit in December 2020 that Bill McSpadden, principal verification engineer at Seagate Technology, gave on the challenges and experiences his team faced in the verification of two custom RISC-V processor cores. While a technical presentation at a technical conference may not be…

The DVCon 2021 edition of Siemens EDA Verification Horizons.

Verification Horizons


The open standard ISA of RISC-V allows SoC developers to also build or modify a processor core optimized to the application requirements. The SoC verification tasks are adapting to address the significant increases in complexity. This article covers the 6 key components of RISC-V processor…

The actual time may be more of a fuzzy risk assessment than a clear demarcation.

Semiconductor Engineering


Even with the billions of dollars spent on R&D for EDA tools, and tens of billions more on verification labor, only 30% to 50% of ASIC designs are first time right, according to Wilson Research Group and Siemens EDA.
Even then, these designs still have bugs. They’re just not catastrophic enough to cause a re-spin. This means more efficient verification is needed. Until…

OpenHW Processor DV Flow with Imperas RISC-V Golden Reference Model


The RISC-V ISA (Instruction Set Architecture) permits a range of possibilities for processor implementation with a modular approach for standard and custom extensions. In addition, implementations may be shared commercially or as open-source, and adopters beyond the original design team can use these directly or as a basis for further modifications and…