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Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

OpenHW article: OpenHW Industrial-Grade Verification for Open-Source CORE-V IP Cores

This brief outline gives an overview of the open methodology and standards-based environment for the verification of the RISC-V based open-source CV32E40P core.

The OpenHW Group - Proven Processor IP

Open-source has two attractive aspects, typically the freedom to modify and adapt the base design offers flexibility beyond the more constrained options with commercial solutions. Secondly, the price - at least the upfront investment is just the time and effort to download and review the base features and capabilities. With the success of open-source software projects, there is increasing interest in open-source hardware and reusable IP for custom SoCs. While the IP selection and decision process has many factors, the main difference between commercial and open-source options might be simplified to a risk assessment of the quality of the deliverables. Software and hardware share some similarities as engineering projects, but a hardware project typically has a cost of manufacture, which drives the requirement for verification - this is especially true for SoC prototypes…

To read the full article published by the OpenHW Group, click here.
 

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Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

NSITEXE’s RISC-V Success Using ImperasDV and Cadence

NSITEXE’s RISC-V Success Using ImperasDV and Cadence

RISC-V Custom Instruction Flow Application Note

Comments

  • John Min, Director, Processor Technology Marketing

    Imagination Technologies

    MIPS Warrior CPUs provide industry leading feature sets, performance, area and power consumption.  Partnering with Imperas to provide models in their innovative virtual platform tools provides a huge advantage to MIPS users. These models, together with Imperas’ new Extendable Platform Kits (EPKs) that let users run high-speed simulations of MIPS-based SoCs on any suitable PC - can benefit MIPS customers and anyone developing software for MIPS platforms. It is an additional benefit to our users to enable them to use the Codescape debugger for software development on both virtual platforms and hardware platforms.

  • Krystian Bacławski, Professor

    Institute of Computer Science at University of Wroclaw

    OVPsim beats QEMU in fidelity in CPU simulation - its determinism and speed were pretty impressive. OVPsim configurability is a big advantage as well. We were able to configure low-level CPU features, thanks to comprehensive documentation. I was also enthusiastic about the machine description file. It was easy to connect a missing interrupt signal we needed.