x

Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

SemiEng: IP Industry Transformation

Design IP has played a pivotal role in the creation of today’s complex SoC, but that role keeps changing. Each change places new demands on IP suppliers.

Semiconductor Engineering

 

The design IP industry is developing an assortment of new options and licensing schemes that could affect everything from how semiconductor companies collaborate to how ICs are designed, packaged, and brought to market.
The IP market already has witnessed a sweeping shift from a “design once, use everywhere” approach, to an “architect once, customize everywhere” model, in which IP is highly configurable and customizable and the focus is on domain-specific optimization. But as chips become increasingly complex, and as new types of IP and licensing models continue to gain ground — especially on the processor side with RISC-V — more changes are coming. The big question now is which of those changes will make a lasting impact, and who will be the winners and losers as a result…

 

To read the full Semiconductor Engineering article by Brian Bailey, click here.


##

Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

Using OVP Fast Processor Models with OVPsim and other simulators

RISC-V Processor Verification: ImperasDV with Synopsys VCS and Verdi Application Note

NSITEXE’s RISC-V Success Using ImperasDV and Cadence

Comments

  • Josh Scheid, Head of Design Verification

    Ventana Micro Systems Inc

    At Ventana, our teams of developers are building the foundational processor IP and chiplet building blocks that will enable a step change in performance for the most demanding compute workload markets.

    Our verification strategy is to exercise the RISC-V based processors across the most demanding scenarios and are using Imperas RISC-V vector test suites in addition to the Imperas golden reference model in our verification environment.

  • Frank Poppen, Researcher

    OFFIS - Institute for Information Technology of Germany

    OVP was selected because of the ease with which models are built and the flexibility in interfacing to other tools. The availability of the ARM processor model we needed, and the open source nature of the OVP models, were also important factors.