New memory approaches and challenges in scaling CMOS point to radical changes — and potentially huge improvements — in semiconductor designs.
We take many things in the semiconductor world for granted, but what if some of the decisions made decades ago are no longer viable or optimal? We saw a small example with finFETs, where the planar transistor would no longer scale. Today we are facing several bigger disruptions that will have much larger ripple effects.
Technology often progresses in a linear fashion. Each step provides incremental improvement over what existed before, or to overcome some new challenge. Those challenges come from a new node, new physical effect, or limitation, etc. While this works very well, and many of the individual steps are brilliant, it is building on a house of cards in that if something at the base were to fundamentally change, the ripple effects throughout the design, implementation, and verification can be very significant…
To read the full Semiconductor Engineering article by Brian Bailey, click here.