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Imperas and Industry Articles

Abstraction is the key to custom processor design and verification, but defining the right language and tool flow is a work in progress.

Semiconductor Engineering

 

High-quality RISC-V implementations are becoming more numerous, but it is the extensibility of the architecture that is driving a lot of design activity. The challenge is designing and implementing custom processors without having to re-implement them every time at the register transfer level (RTL…

Technologies must evolve to keep up with changing demands, and emulation is no exception.

Semiconductor Engineering

 

Emulation is now the cornerstone of verification for advanced chip designs, but how emulation will evolve to meet future demands involving increasingly dense, complex, and heterogeneous architectures isn’t entirely clear.
EDA companies have been investing heavily in emulation, increasing capacity, boosting performance, and adding new…

The cloud cements its role in embedded hardware design.

Engineering and Technology

In the summer of 2018, professors John Hennessy and David Patterson declared a glorious future for custom hardware. The pair had picked up the Association for Computing Machinery’s Turing Award for 2017 for their roles in the development of the reduced instruction set computer (RISC) architectural style in the 1980s. 
Towards the end of their acceptance speech, Patterson pointed to the…

Automatic mapping of software onto existing hardware, or using software to drive hardware design, are highly desired but very difficult.

Semiconductor Engineering

 

For the past 20 years, the industry has sought to deploy hardware/software co-design concepts. While it is making progress, software/hardware co-design appears to have a much brighter future. In order to understand the distinction between the two approaches, it is important to define some…

The open ISA of RISC-V means any SoC developer can now design a custom processor - moving the verification task from a few specialist suppliers to all SoC developers. This article looks at the industrial-grade verification and open methodology as used by the OpenHW verification working group.

RISC-V Processor Design Verification (DV)

One of the appealing things about open-source is that it invites…

New approaches emerge as demand for improved power and performance overwhelm design tools.

Semiconductor Engineering

 

The semiconductor ecosystem is at a turning point for how to best architect the CPU based on the explosion of data, the increased usage of AI, and the need for differentiation and customization in leading-edge applications.

In the past, much of this would have been accomplished by moving to the next process node. But with the benefits from…

Designs are getting bigger, verification runs longer, and every stage of development and deployment provides valuable data — if you can find it.

Semiconductor Engineering

 

The amount of data that could be kept for every design is gargantuan, but even that may not be enough these days as lifecycle management, continuous verification, regulatory requirements, and globalization add to the data that needs to be stored.

But data has no value if it cannot…

As localized processors become more powerful, what works best where?

Semiconductor Engineering

 

Increasing amounts of processing are being done on the edge, but how the balance will change between what’s computed in the cloud versus the edge remains unclear. The answer may depend as much on the value of data and other commercial reasons as on technical limitations.

The pendulum has been swinging between doing all processing in the cloud to doing…

The IC industry is struggling with blurring lines between different disciplines as chips are more tightly integrated with software in packages and systems.

Semiconductor Engineering

 

Complexity in hardware design is spilling over to other disciplines, including software, manufacturing, and new materials, creating issues for how to model more data at multiple abstraction levels.

Challenges are growing around which abstraction level to use for a particular stage of the…