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Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

How To Build Resilience Into Chips

Heterogeneous designs, customization, and increasing complexity open doors for hardware errors.

Semiconductor Engineering

 

Disaggregating chips into specialized processors, memories, and architectures is becoming necessary for continued improvements in performance and power, but it’s also contributing to unusual and often unpredictable errors in hardware that are extremely difficult to find….
 

To read the full Semiconductor Engineering article by Ed Sperling and Ann Mutschler, click here.


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Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

Using OVP Fast Processor Models with OVPsim and other simulators

RISC-V Processor Verification: ImperasDV with Synopsys VCS and Verdi Application Note

NSITEXE’s RISC-V Success Using ImperasDV and Cadence

Comments

  • Nagra Kudelski

    Nagra, part of the Kudelski Group, a global leader in digital security and convergent media solutions for the delivery of digital and interactive content stated: "At NAGRA, we have adopted the Imperas virtual platform-based software development and test tools for our application and firmware teams. The simulator performance, and the tools for software analysis, have added significant value to our daily Agile Continuous Integration (CI) methodology. Our view is that software simulation is mandatory to reach metrics required for high quality secured products."

  • Krystian Bacławski, Professor

    Institute of Computer Science at University of Wroclaw

    OVPsim beats QEMU in fidelity in CPU simulation - its determinism and speed were pretty impressive. OVPsim configurability is a big advantage as well. We were able to configure low-level CPU features, thanks to comprehensive documentation. I was also enthusiastic about the machine description file. It was easy to connect a missing interrupt signal we needed.