RISC-V Summit 2022 Conference talk
RISC-V International develops and maintains the RISC-V ISA specification and provides basic architectural tests to confirm if users have read the specification. OpenHW Group develops and maintains open-source RISC-V processor cores and develops a unified open source testbench and verifies the cores to industrial quality levels. Conceptually, verification ensures you have implemented what you have specified for your design, and the compliance testing ensures you have met the ISA specification. There is a continuum of testing. This talk discusses the boundary between compliance and design verification, and the different technologies and tools required for each area. Also, the new projects in OpenHW Group are introduced that are moving the RISC-V Verification open ecosystem forward in the areas of Functional Coverage, Verification Standards, and Core quality with quantitative measurement for use with both commercial and open-source projects. An example illustrates the new open standard RISC-V Verification Interface (RVVI) Virtual Verification Peripheral definitions (VVP) and use in compliance testing of privilege mode items such as asynchronous interrupts and debug mode requests.
Simon Davidmann, CEO at Imperas Software and Verification Task Group Chair at OpenHW Group
Allen Baum of Esperanto Technologies, Inc., and Chair of the RISC-V International Architecture Test SIG
The video of this presentation is available on YouTube.