The design freedoms of RISC-V offer developers flexibility for innovation – now processor IP verification quality is also a flexible option.

The RISC-V open standard ISA (Instruction Set Architecture) offers developers the opportunity to configure the features and functions of a custom processor to uniquely address their target end application needs and requirements. RISC-V has a modular structure with…

Companies that invest in their employees’ education often get rewarded with more productive and happier workers.

Continuous education is essential for engineers, but many companies don’t recognize the value or they are unwilling to provide the necessary resources.
This should be a line of questioning before every new hire makes the decision about where they want to work, because it not only affects their future career, but…

Imperas simulation technology and reference model available for free, including test suites for basic processor hardware verification and compliance testing.

Oxford, UK – July 19th, 2021 – Imperas Software Ltd., the leader in RISC-V processor verification technology, announces the latest updates to riscvOVPsimPlus with support for the near ratified P extension…

Imperas simulation technology and RISC-V reference models updated to cover the RISC-V P Extension for SoC architecture exploration and early software development.

Oxford, UK – July 12th, 2021 – Imperas Software Ltd., the leader in virtual platforms and high-performance software simulation, today announced that Andes Technology Corp., a leading supplier of performance-efficient and extensible 32/64-bit RISC-V CPU cores and a Founding…

Time spent in debug is unpredictable. It consumes a large portion of the development cycle and can disrupt schedules, but good practices can minimize it.

Debug often has been labeled the curse of management and schedules. It is considered unpredictable and often can happen close to the end of the development cycle, or even after – leading to frantic attempts at work-arounds. And the problem is growing…

To read the full …

Imperas simulation technology and RISC-V reference models now available pre-integrated within Valtrix STING for advanced RISC-V Processor Verification.

Oxford, UK – June 30th, 2021 – Imperas Software Ltd., the leader in RISC-V processor verification technology, today announced a multi-year distribution and support agreement with Valtrix Systems, provider of design verification products for…

SiFive qualifies models that are based on Imperas proprietary simulation technology — now available for SoC architecture exploration and early software development.

Oxford, UK – June 29th, 2021 – Imperas Software Ltd.,the leader in virtual platforms and high-performance software simulation, today announced that SiFive, Inc., the industry leader in RISC-V processors and silicon solutions,…

Automakers shifting to HPC chips for improved performance and lower system cost.

Automotive architectures are evolving quickly from domain-based to zonal, leveraging the same kind of high-performance computing now found in data centers to make split-second decisions on the road.

This is the third major shift in automotive architectures in the past five years, and it’s one that centralizes processing using 7nm and 5nm technology, specialized accelerators,…

The EDA ecosystem is in the early stages of pivoting to the cloud, but not everything will move there.

As EDA is moving to the cloud in fits and starts as tool vendors sort out complex financial models and tradeoffs while recognizing a potentially big new opportunity to provide unlimited processing capacity using a pay-as-you-go approach.

By all accounts, a tremendous amount of tire-kicking is happening now as EDA vendors and users delve…