SiFive have qualified the Imperas models for the full range of the SiFive processor Core IP Portfolio, see the full announcement at this link.
The Imperas OVP models for SiFive processor IP cores can also be combined with the Imperas virtual platform development and simulation Dev tools and M*SDK advanced multicore software development kit.
The Imperas OVP model library for SiFive professor IP includes:
SiFive Performance Family: cores for performance application processors
P270 – Efficient performance, RISC-V RV64GCV ISA, multi-core- and Linux-capable
P550 – High performance, RISC-V RV64GC ISA, multi-core- and Linux-capable
SiFive Intelligence Family: cores for AI/ML SoCs
X280 – RISC-V RV64GCV ISA, Intelligence Extensions, multi-core- and Linux-capable
SiFive Essential Family: cores for 32bit and 64bit embedded systems
E Series: 32-bit embedded cores for MCU, edge computing, AI, IoT
E20, E21, E24, E31, E34, E51, E76
S Series: 64-bit embedded cores for Storage, AR/VR, machine learning
S21, S51, S54, S76
U Series: 64-bit application processors for Linux, datacenter, network baseband
More information about Imperas OVP models for SiFive can be found at OVPworld