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Imperas updates Free reference model riscvOVPsimPlus with new RISC-V P (SIMD/DSP) extension and Architectural Validation Test Suites

Imperas simulation technology and reference model available for free, including test suites for basic processor hardware verification and compliance testing.

riscvOVPsimPlus for RISC-V P (Packed SIMD/DSP) Extension

Oxford, UK – July 19th, 2021 – Imperas Software Ltd., the leader in RISC-V processor verification technology, announces the latest updates to riscvOVPsimPlus with support for the near ratified P extension and architectural validation test suites. The P (or Packed SIMD/DSP) extension is a significant addition to the flexibility of the modular RISC-V ISA (Instruction Set Architecture); it supports real-time data processing applications as part of the main processor pipeline without the need for the associated inefficiencies of a co-processor. For processor hardware verification, a basic test suite helps ensure implementations have a basic software level compatibility to the new P extension as a reference to the developers’ interpretation of the written specification.

riscvOVPsimPlus is a popular free ISS (Instruction Set Simulator) that is an envelope model that can be configured to cover all of the ratified RISC-V specifications and standard extensions. Also included are several Architectural Validation Test Suites, which form a basic test plan for software level compatibility within the specification definitions. The Imperas models are available as open-source and licensed under the Apache 2.0 flexible open-source license. All models, virtual platforms and example models are provided to the community via the Open Virtual Platforms website The Imperas commercial simulation technology and products are based on the freely available open-standard public OVP APIs.

The Imperas RISC-V architectural validation test suites are collections of tests focused on specific ISA extensions that provide basic testing of instruction execution and usage of the full range of operands with a set of representative data values. They are not a substitute for full detailed tests suites for design verification but provide detailed coverage reports of the different parts of the architectural specification tested. The currently released test suites available free on the OVP website now include P SIMD/DSP, K-crypto, V-vector, B-bitmanip, F, D, I, M, and C.


“Flexibility within a framework of compatibility is the essential foundation of the RISC-V ISA,” said Chuanhua Chang, Andes Technology Corporation, Chair of RISC-V International P Extension Task Group. “The RISC-V P extension defines a rich set of integer SIMD/DSP instructions operating on existing integer registers to support complex data processing within the constraints of real-time applications. However, the hardware specification is just the start - adoption and success depend on the software ecosystem, which is supported with the reference models and test suites from Imperas.”


“By combining SIMD/DSP functionality within the RISC-V ISA offers the ideal balance for performance, flexibility and efficiency,” said Wei Wu, PLCT Lab, ISCAS, Vice-Chair of RISC-V International P Extension Task Group. “The Imperas RISC-V reference model provides the ideal starting point to explore and develop software algorithms based on the new RISC-V P extension.”


“The Imperas simulation technology and RISC-V reference models are in active use in some of the most complex RISC-V verification projects,” said Simon Davidmann, CEO at Imperas Software Ltd. “RISC-V is changing the design process as new design exploration can start without many of the traditional barriers. The adoption of riscvOVPsimPlus with the new RISC-V P extension support helps provide clarification of the specification boundary as a useful guideline for innovation in new processor designs.”


About RISC-V Processor Verification IP
The free riscvOVPsimPlus package including the test suites and functional coverage analysis are now available on OVPworld at riscvOVPsimPlus solution is an entry ramp for development and verification and includes a proprietary freeware license from Imperas, which covers free commercial use as well as academic use. The simulator package also includes a complete open-source model licensed under the Apache 2.0 license.

The RISC-V processor Verification IP, example test benches and any customer-specific test suites are Imperas commercial solutions. Imperas also provides solutions for developers of more advanced RISC-V designs, who need multicore, or custom instruction support and advanced verification techniques. Imperas also offers a rich library of models for virtual platforms as used in early software development and hardware verification, including methodologies around continuous integration and regression using ‘virtual’ test farms, plus support for hybrid verification platforms with hardware emulators provided by Cadence Palladium, Siemens EDA Veloce, and Synopsys Zebu.

The Imperas simulation technology and reference models support the full spectrum of RISC-V processor verification requirements from a basic functional test, routine specification compliance, coverage driven verification, right through to the latest step-and-compare flows. The step-and-compare methods used for complex designs cover both asynchronous events and also, when integrated into a UVM SystemVerilog test bench, provide a seamless environment for efficient debug and analysis. To learn more about the options for RISC-V verification, visit


About Imperas

Imperas is the leading provider of RISC-V processor models, hardware design verification solutions, and virtual prototypes for software simulation. Imperas, along with Open Virtual Platforms (OVP), promotes open source model availability for a spectrum of processors, IP vendors, CPU architectures, system IP and reference platform models of processors and systems ranging from simple single core bare metal platforms to full heterogeneous multicore systems booting SMP Linux. All models are available from Imperas at and the Open Virtual Platforms (OVP) website at

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