Imperas with Andes and UltraSoC are co-hosting a webinar series on RISC-V, this latest installment is on optimizing RISC-V with Custom Instructions - Recording now available on-line!
Imperas Software Ltd., the leader in high-performance software simulation and virtual platforms, today announced together with Andes and UltraSoC the latest webinar for SoC designers on the flexibility of RISC-V in SoC designs for 5G, AI, AR/VR, and IoT with optimized extensions and custom instructions.
Outline: Join the Andes, Imperas, and UltraSoC webinar on the flexibility of RISC-V in SoC designs for 5G, AI, AR/VR, and IoT with optimized extensions and custom instructions. Starting with architectural exploration to profile applications and identify candidate instructions, then details of the design flow to implement and verify new extensions, and use on-chip instrumentation for debug, analysis and lifecycle management. RISC-V is opening up new aspects of design freedoms with optimized solutions beyond the boundary of standard processor core roadmaps. Domain specific optimizations offer just the right balance between hardware efficiency and software flexibility. Start exploring your next project with the flexibility of RISC-V and optimized extensions.
The Agenda will cover the key prototype phases of RISC-V based SoC design:
• Imperas: Architectural Exploration with Software driven early prototype analysis with virtual platforms.
• Andes: Processor Core Configuration with Optimized extensions for Cores and for Processor sub-systems.
• UltraSoC: On-Chip Instrumentation with Debug & Trace, and On-Chip performance monitors for lifecycle analysis.
The webinar will conclude with a live hosted Q&A session with all the presenters as a group discussion.
When: Tuesday September 29th 2020
8am - San Jose, Bay Area (PDT)
Recording now available at this link.
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