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Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

RISC-V Summit 2021 - Lightning talk: Open-Source RISC-V Cores with Industrial strength verification

Abstract:

This case study explores the background, development and implementation of the OpenHW verification environment for CV32E40P known as “core-v-verif”. Since the goal of the project is to support adoption on of an open-source IP core, the initial deliverable quality is not the only concern. One attractive aspect of an open-source core is the potential for adopters to modify, adapt, or extend the base core features. Thus, the verification plan needs to anticipate the future use case with flexibility built in to the testbench to accommodate future modifications as adopters extend the core features.

Co-Author:       Simon Davidmann – Imperas Software
Co-Author:       Lee Moore – Imperas Software

The video of this presentation is available at this link.
 

 

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Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

RISC-V Processor Verification: ImperasDV with Synopsys VCS and Verdi Application Note

Using OVP Fast Processor Models with OVPsim and other simulators

NSITEXE’s RISC-V Success Using ImperasDV and Cadence

Comments

  • Don Smith, Vice President Engineering

    MIPS, Inc.

    At MIPS we are experienced in bringing advanced computing technology, such as hardware multi-threading, to market as applications-class processors.

    As part of the strategic move to RISC-V, we fully appreciate the needs, implications and requirements for a high-quality verification solution. The Imperas Reference Model enables lock-step-compare with asynchronous events which is the foundation of our SystemVerilog testbench and verification methodology.

  • Shubhodeep Roy Choudhury, Managing Director & Co-founder

    Valtrix Systems

    As the leading provider of commercial RISC-V Instruction Stream Generators, it is essential for verification standards for test benches and verification IP reuse to evolve.

    Adopting RVVI virtual peripherals provides additional flexibility and efficiency for our flagship verification product STING to target asynchronous event verification, which is essential for quality RISC-V processor functional design verification