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Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

A quick look at the DAC 2022 conference program

The latest posts on the EDA, IP and SoC Industries

 

EDACafe

 

The Design Automation Conference is back to its usual summer timeframe – again at the Moscone Center in San Francisco – with over one hundred exhibitors and a rich conference program that covers a wide range of topics including artificial intelligence, autonomous systems, RISC-V, security, embedded systems and more. Here we will briefly highlight some of the conference content more directly related to EDA, referring readers to the conference program for the detailed schedule…

 

To read the full EDACafe article by Roberto Frazzoli, click here.


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Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

Using OVP Fast Processor Models with OVPsim and other simulators

NSITEXE’s RISC-V Success Using ImperasDV and Cadence

Using OVP Fast Processor Models with OVPsim and other simulators

Comments

  • Paul Cunningham, GM System & Verification Group

    Cadence

    By integrating our Xcelium Logic Simulator with Imperas's RISC-V verification technology, we've empowered NSITEXE to design the next-generation of its Akaria processors, which are optimized for safety-critical applications and compliant with the ISO 26262 ASIL D standard.

    Our work together exemplifies Cadence’s commitment to collaboration and innovation to support our customers in the rapidly evolving semiconductor industry.

     

  • Mike Ingster, President and Founder

    Quantum Leap Sales

    Imperas solutions for early software development have never been more appropriate with development schedules more critical than ever. We believe that simulation-based verification is fast becoming an essential requirement in complex SoCs, and together with advanced debug and analysis tools for many-core and heterogeneous designs will greatly reduce development schedules for next generation devices.