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Imperas to present at the WISH Conference, September 13 2022

Imperas to present an overview of RISC-V processor verification for open-source IP cores

WISH (Women in Semiconductor Hardware) Conference

Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced their participation at the WISH (Women in Semiconductor Hardware) Conference. GSA (Global Semiconductor Alliance) has established its Women’s Leadership Initiative (WLI) and the technical conference WISH. The annual event features technical presentations on the latest updates for the design and development of semiconductor ICs and SoCs.

‘Open-Source Has a Great Price, But Verification Adds the Real Value’
•    Speaker:     Manny Wright – Imperas Software
•    When:         September 13, 2022 10:50am – Santa Clara Convention Center, California

Abstract: 
RISC-V adopters are exploring processor design freedoms enabled by the open standard ISA. These design freedoms are also driving the interest in open-source hardware. The OpenHW RISC-V cores are open-source, free is a great price but the real value is in the verification to industrial grade standards for commercial adoption. This talk with highlight the innovations in RISC-V processor verification that complements the design freedoms of the open standard ISA.

 

About the WISH Conference
For more information see this link.
 

 

 

About Imperas

For more information about Imperas, please see www.imperas.com. Follow Imperas on LinkedIn, twitter @ImperasSoftware and YouTube.

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Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

ARM TrustZone Platform Modeling Application Note

ARM TrustZone Platform Modeling Application Note

Using OVP Fast Processor Models with OVPsim and other simulators

Comments

  • Allen Baum, Chair of the RISC-V International Architecture Test SIG

    Esperanto Technologies, Inc.

    A key part of the RISC-V privilege specification that is fundamental for OS and application security is the PMP feature.

    Enabling its correct operation is essential for security applications, and the Imperas PMP test suites are a valuable contribution to the RISC-V compatibility and verification community.

  • Mark Jensen, Director, Processor Platforms Marketing

    Xilinx

    Imperas, with its OVP Fast Processor Models and software development tools, is addressing key issues in software development for embedded systems. We are excited to work with Imperas to ensure that high quality models are easily available to our customers worldwide, helping them to develop and test software faster and more efficiently using virtual platforms.