Imperas and Metrics joining CHIPS Alliance to help drive the verification of RISC-V Open ISA implementations
SAN FRANCISCO – June 18, 2019 – CHIPS Alliance, the leading consortium advancing common, open hardware for interfaces, processors and systems, today announced Imperas and Metrics are joining the organization and the Verification Working Group. Imperas is an independent provider of processor simulation technology and tools for virtual platforms and analysis tools for multicore SoC software development. Metrics leads the cloud-based solutions for SoC designers with hardware simulation for both design management flexibility and on-demand capacity. The CHIPS Alliance welcomes Imperas and Metrics among its current members Antmicro, Esperanto Technologies, Google, SiFive, and Western Digital.
CHIPS Alliance is a project hosted by the Linux Foundation to foster a collaborative environment to accelerate the creation and deployment of open SoCs, peripherals and software tools for use in mobile, computing, consumer electronics, and Internet of Things (IoT) applications. The CHIPS Alliance project hosts and curates high-quality open source Register Transfer Level (RTL) code relevant to the design of open source CPUs, RISC-V-based SoCs, and complex peripherals for Field Programmable Gate Arrays (FPGAs) and custom silicon.
Imperas provides reference processor models for verification of processors and SoC’s and will be contributing to the CHIPS Alliance working group on verification. Planned contributions will include enhanced interfaces and design flow methodologies to the riscvOVPsim ISS (Instruction Set Simulator) for RISC-V processor IP verification and compliance. riscvOVPsim is free and available for download on GitHub as part of the latest RISC-V compliance test suite and framework, available on GitHub at https://github.com/riscv/riscv-compliance
Metrics is the first cloud platform for ASIC and complex FPGA design verification. The company provides design teams with on-demand simulation resources, a modern continuous integration workflow, a pricing by-the-minute business model and unique development flexibility. Metrics develops innovative products powered by a cross-functional team that includes simulation technologists, IC design verification experts, and modern cloud software developers.
“Within the RISC-V community and ecosystem Imperas has made many contributions to customer and community projects and also released a free RISC-V reference simulator on GitHub, while Metrics has pioneered a cloud-based approach that enables infinite hardware simulation capacity that changes the nature of semiconductor verification use models,” said Zvonimir Bandic, senior director of next-generation platforms architecture at Western Digital and Chairman, CHIPS Alliance. “With Imperas joining CHIPS Alliance, we welcome their contributions within the verification task group to help the industry-wide efforts to ensure quality IP is available to all adopters of RISC-V. Metrics’ contributions to verification infrastructure will provide a modern approach to RISC-V cores, peripherals, and complex IP block development.”
“Imperas is pleased to join the CHIPS Alliance and support the continuing efforts to improve verification for all RISC-V implementers and SoC designers,” said Simon Davidmann, CEO of Imperas Software. “Open ISA’s are enabling new approaches and innovations in processor architectures that will require broad community support to address the verification challenges of next generation domain specific optimized devices.”
“Metrics was founded with an open platform philosophy that has allowed the company to form many valuable relationships that drive next-generation verification approaches,” said Doug Letcher, CEO, Metrics. “In joining CHIPS Alliance, we are excited to help and support industry wide collaborations for verification that are essential for the next generation of devices.”
“CHIPS Alliance has seen a tremendous wave of interest and support since it was first announced just a few months ago,” said Ted Marena, Interim Director CHIPS Alliance. “We are pleased to welcome Imperas and Metrics as our latest members and both will be in attendance at the inaugural workshop on June 19, 2019 at Google at 111 W. Java Drive, Sunnyvale, Calif.”
The CHIPS Alliance community includes technology developers and contributors supported by a Board of Directors and a Technical Steering Committee. Its initial plans focus on establishing a curation process aimed at providing the FPGA and chip community access to high-quality, enterprise grade hardware.
Imperas is revolutionizing the development of embedded software and systems and is the leading provider of RISC-V processor models and virtual prototype solutions. Imperas, along with Open Virtual Platforms (OVP), promotes open source model availability for a spectrum of processors, IP vendors, CPU architectures, system IP and reference platform models of processors and systems ranging from simple single core bare metal platforms to full heterogeneous multi-core systems booting SMP Linux. All models are available from Imperas at www.imperas.com and the Open Virtual Platforms (OVP) website.
Metrics, headquartered in Ottawa, Ontario, Canada, is the first true cloud-based platform for ASIC and complex FPGA Design Verification. The Metrics Platform provides an infinitely scalable design verification workflow together with advanced simulation technology, which reduces infrastructure waste and enables better engineering efficiency. https://metrics.ca/
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