RISC-V Summit 2022 Tutorial
As experienced SoC design verification (DV) teams take up the RISC-V processor verification challenge new approaches and techniques are required over traditional top-down block level testing. RISC-V verification plans need to address the full complexity of RISC-V features including Vector extensions, PMP security, multi-hart, multi-issue plus other advanced features. Coverage metrics have been the traditional approach to ensure a design is ready for release to prototype manufacture. For a complete RISC-V verification plan, coverage analysis needs to include all the complexities of the privilege specification including processor modes and asynchronous events. This tutorial presents a structured approach to RISC-V processor verification. It covers the basic steps from setting up an initial verification environment (testbench) to using the latest open standards for VIP (Verification IP) and the resources available within the RISC-V verification ecosystem. It highlights the importance of a verification plan and metric-driven verification for RISC-V processor designs that are destined for silicon production.
Lee Moore, Imperas Software Ltd.
Aimee Sutton, Imperas Software Ltd.
The video of this presentation is available on YouTube.