Showing that a processor core adheres to a specification becomes more difficult when the specification is extensible.
The open-standard RISC-V instruction set architecture (ISA) continues to gain momentum, but the flexibility of RISC-V creates a problem—how do you know if a RISC-V implementation fits basic standards and can play well with other implementations so they all can run the same ecosystem? In addition, how do you ensure...
An interesting article by Brian Bailey. To read the article with comments by Simon Davidmann and Kevin McDermott of Imperas Software, click here.