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Revolutionizing Embedded Software Development

RISC-V Summit 2021 - SW Keynote talk: Is hardware/software co-design for applications now a reality with RISC-V?

Abstract:

RISC-V Vector instructions offer significant flexibility and options to configure a hardware accelerator for applications such as Datacenters and AI. Following initial cloud-based development with extensive real-world datasets, the migration to a hardware accelerator array with RISC-V vectors is redefining the software driven approach to hardware design.
This talk highlights SoC architectural exploration with multicore arrays and optimized RISC V processors to support early software development for vector accelerators. It introduces some of the challenges and discusses different approaches being adopted in the community/industry.

Co-Author:       Kevin McDermott – Imperas Software
Co-Author:       Simon Davidmann – Imperas Software

The video of this presentation is available at this link.
 

 

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Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

Using OVP Fast Processor Models with OVPsim and other simulators

RISC-V Custom Instruction Flow Application Note

Using OVP Fast Processor Models with OVPsim and other simulators

Comments

  • Vijay Krishnan, General Manager, RISC-V Ventures

    Intel

    The adoption of RISC-V is at an inflexion point across multiple markets and applications, and Intel fully appreciates that a healthy software ecosystem is critical for this new ISA to be successful.

    The availability of Imperas RISC-V reference models for the Professional Edition of Intel Pathfinder for RISC-V further strengthens the tools available to developers as new silicon designs move from concept to production.

  • Rishiyur Nikhil

    CTO Bluespec Inc. and Chair of RISC-V Formal Task Group

    The RISC-V ISA Formal Spec Task Group will produce a Formal Specification for the RISC-V ISA. We see the introduction of riscvOVPsim as an excellent reference platform to test and verify with.