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Revolutionizing Embedded Software Development

RISC-V Summit 2021 - SW Keynote talk: Is hardware/software co-design for applications now a reality with RISC-V?

Abstract:

RISC-V Vector instructions offer significant flexibility and options to configure a hardware accelerator for applications such as Datacenters and AI. Following initial cloud-based development with extensive real-world datasets, the migration to a hardware accelerator array with RISC-V vectors is redefining the software driven approach to hardware design.
This talk highlights SoC architectural exploration with multicore arrays and optimized RISC V processors to support early software development for vector accelerators. It introduces some of the challenges and discusses different approaches being adopted in the community/industry.

Co-Author:       Kevin McDermott – Imperas Software
Co-Author:       Simon Davidmann – Imperas Software

The video of this presentation is available at this link.
 

 

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Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

RISC-V Processor Verification: ImperasDV with Synopsys VCS and Verdi Application Note

ARM TrustZone Platform Modeling Application Note

NSITEXE’s RISC-V Success Using ImperasDV and Cadence

Comments

  • Duncan Graham

    University Program Manager, Imperas Software

    The Imperas University Program encourages participation in the embedded systems community in three ways: use on research projects, use in the classroom, and sharing of virtual platform models through the Open Virtual Platforms (OVP) Library.

  • Shubhodeep Roy Choudhury, Managing Director & Co-founder

    Valtrix Systems

    As the leading provider of commercial RISC-V Instruction Stream Generators, it is essential for verification standards for test benches and verification IP reuse to evolve.

    Adopting RVVI virtual peripherals provides additional flexibility and efficiency for our flagship verification product STING to target asynchronous event verification, which is essential for quality RISC-V processor functional design verification