Imperas at Hot Chips 2019 – Demos of RISC-V Compliance and Verification – August 19-20 2019
Imperas will be conducting demonstrations around the unique requirement and challenges facing RISC-V processor architects and core developers:
- RISC-V Processor verification flow based on the Google RISC-V Instruction Stream Generator and comparisons between RTL cores and Imperas reference models.
- The first IA simulator to support the new RISC-V Vector, and Bit Manipulation extensions.
- Latest compliance testing with the official RISC-V Foundation compliance suite.
- Profiling and analysis of RISC-V custom instructions from concepts analysis based on application code, profiling, debug, analysis, documentation and final model development.
- Programmers view models and virtual platforms for early software development as new core implementations and SoC’s are still in development.
Please email firstname.lastname@example.org to meet with Imperas at HOT CHIPS!
About HOT CHIPS 2019
Since it started in 1989, HOT CHIPS has been known as one of the semiconductor industry’s leading conferences on high-performance microprocessors and related integrated circuits. The conference is held once a year in August in the center of the world’s capital of electronics activity, Silicon Valley.
- Where: Stanford University Campus, San Francisco, California, USA
- When: August 18-20, 2019.
For more information see http://www.hotchips.org/
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