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Imperas to present updates on the RISC-V Ecosystem that supports new design innovations with RISC-V via Flexibility With Compatibility
Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced their participation at the next New York City RISC-V Group Meeting November 16, 2022. At the previous event, speakers described how engineers across different fields can get involved in RISC-V with real world use cases and examples. At this hybrid event, with an in-person element at The Cooper Union for the Advancement of Science and Art, speakers will describe their latest research and development involving RISC-V.
The RISC-V Ecosystem: Building In Flexibility With Compatibility
Larry Lapides, Imperas Software
For hardware developers RISC-V offers the flexibility to optimize a processor to address target applications in new and unique ways. RISC-V also offers new opportunities to select IP core options from the commercial IP companies, open-source projects, and also the freedom to construct a new implementation based on the open standard ISA (Instruction Set Architecture).
Traditional software ecosystems have developed around a common set of hardware configurations, but RISC-V offers unique flexibility. Will this flexibility lead to fragmentation and chaos?
This presentation looks at the RISC-V ecosystem, both the successes and areas with work still required. Mass adoption is dependent of the efficiencies of scale that in turn depend on compatibility while supporting the value added-optimizations and differentiation. Has the RISC-V approach, based on ecosystem-first strategy, built-in sufficient support for flexibility with compatibility?
When: Wednesday November 16th 2022 at 5:45pm EST
Where: Hybrid Event
The Cooper Union for the Advancement of Science and Art
41 Cooper Square
New York, 10003
Free registration and more details are available at this link.
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Comments
Vijay Krishnan, General Manager, RISC-V Ventures
IntelThe adoption of RISC-V is at an inflexion point across multiple markets and applications, and Intel fully appreciates that a healthy software ecosystem is critical for this new ISA to be successful.
The availability of Imperas RISC-V reference models for the Professional Edition of Intel Pathfinder for RISC-V further strengthens the tools available to developers as new silicon designs move from concept to production.
Rick O’Connor, President & CEO
OpenHW GroupThe open RISC-V ISA specification is an excellent starting point and open-source processor IP cores, such as the CORE-V family, have real potential to change the industry.
The high-quality open-source CORE-V CV32E40P core now allows the broadest participation in the RISC-V revolution, the OpenHW MCU Dev/Kit project is just one example of the innovations that can now be developed from the quality foundation provided by the CV32E40P core, having been verified with the CORE-V-VERIF testbench which leverages the Imperas RISC-V golden reference model.