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Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

E&T: Intel leans harder on RISC-V

No more not-invented here for the chip giant when it comes to processor architectures.

Engineering and Technology

Much like IBM after the PC architecture ran away from it and almost collapsed Big Blue’s highly profitable minicomputer and mainframe businesses, Intel has been through some soul-searching in the wake of Arm’s expansion from the world of cellular phones into just about everything else. 
Intel has moved from a company that sued relentlessly to try to maintain control of the instruction set architecture (ISA) that powered the PCs that crippled IBM’s original business to one that now sees or at least claims to see the advantages in an [open standard] ISA that anyone can use to build their own processors. Intel is now one of RISC-V’s biggest fans, launching this week a programme to try to get more chip designers onboard with the architecture….
 

To read the full Engineering and Technology article by Chris Edwards, click here.


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Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

NSITEXE’s RISC-V Success Using ImperasDV and Cadence

NSITEXE’s RISC-V Success Using ImperasDV and Cadence

NSITEXE’s RISC-V Success Using ImperasDV and Cadence

Comments

  • Charlie Hong-Men Su, CTO and Senior VP

    Andes Technology

    The Imperas virtual platform solutions for software development, debug and test, along with their open-source models, comprise an excellent methodology for development of embedded software for SoCs based on V5 AndesCore N25 and NX25 RISC-V processors.

  • Dr. Charlie Su, President and CTO

    Andes Technology Corp.

    RISC-V represents the potential for innovation, and it is the implementation of great ideas that are really generating exceptional results.

    To unlock such potentials, Andes provides the AndeSysC™ environment, an extensible and near-cycle accurate SystemC model library for all AndesCore®. SoC architects can use it to construct a SystemC based virtual platform for performance evaluation of critical code segment and hardware/software co-optimization. ACE technology helps users implement custom functions and instructions, and it directly connects to the AndeSysC™ environment. Now with the close integration with the Imperas fast reference models and tools, design teams can embark on architecture exploration with complete application software for the next generation of domain specific devices with a seamless path to ACE implementation.