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EW20 Paper on Impact of RISC-V Adaptability on SoC Verification Methods


As the RISC-V instruction set architecture (ISA) matures, and SoCs are developed using RISC-V, there is a need to address the new verification challenges of RISC-V based SoCs. For SoCs built using traditional processor cores, the verification tasks are well known, as the starting point is based on the assumption of “known good IP.” The new verification challenges include verification of the RISC-V processor IP; verification of the processing element (PE) containing the RISC-V core(s) (especially relevant in SoCs with a fabric designed for AI processing); connection of the processor itself or the PE to the network on chip (NoC) and multiple PEs communicating through the NoC to each other. In this paper the verification challenges for RISC-V SoCs are presented. Specific verification flows including new test and instruction stream generators, reference models and metrics are presented in detail including the results of using these flows on real processor IP and SoCs.