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Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

Enabling industrial-grade open verification for RISC-V

The open nature of the RISC-V means anyone can design a custom processor - moving the verification task from a few specialist suppliers to all SoC developers. This article looks at the industrial-grade verification and open methodology to support verification of an open-source CV32E40P core.

Embedded

The amount of time, money and effort it takes to design a system-on-chip (SoC) means it is not surprising when engineering teams want to get it right first time. This long-held ideal doesn’t just happen on its own; it takes a lot of test, measurement and verification. Of course, this requires funding and effort, but as most people would agree, spending a little more in the early design phase can save spending much, much more later…

To read the full Embedded Magazine article, click here.


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Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

ARM TrustZone Platform Modeling Application Note

RISC-V Processor Verification: ImperasDV with Synopsys VCS and Verdi Application Note

ARM TrustZone Platform Modeling Application Note

Comments

  • Professor Fernando Gehm Moraes

    Pontifical Catholic University of Rio Grande do Sul, Brazil - PUCRS

    At PUCRS, we use Imperas virtual platforms in projects on multiprocessor SoC modeling, power evaluation, and programmability, as well as computer science graduate program courses on SoCs and research architecture. Our research group (Grupo de Apoio ao Projeto de Hardware, or Hardware Design Support Group), also leverages these tools.

  •  Steve Richmond, Co-chair of the OpenHW Group Verification Task Group

    Silicon Laboratories

    Simulation is central to the entire semiconductor design and verification flow, and while a processor is described in Verilog RTL, the industry standard for testbenches is SystemVerilog.

    The Verification Task Group is addressing the challenges of processor verification using the Imperas RISC-V golden model encapsulated within our UVM SystemVerilog methodologies.