RISC-V Summit 2022 FutureWatch talk
The design freedoms of RISC-V offer systems and SoC developers new flexibility to optimize a processor for the requirements of the target application. Now Architectural Exploration is not just about the configuration of multi-core designs, but the analysis of the application and potential advantages of custom instructions. Custom extension can boost the performance for a target class of operations, or support new multi-core communication methods.
Software development with virtual prototypes is well established, but new to RISC-V is the advantage of these platforms offer to end users migrating legacy applications to the new RISC-V based device, well before silicon is available.
For SoC teams optimizing a RISC-V processor they also need to address the additional challenge of RISC-V verification, open standards such as RVVI (RISC-V Verification Interface) are helping the ecosystem support for standards-based test benches and Verification IP.
This talk highlights the RISC-V models that are unifying the hardware, software, and verification teams across all phases of RISC-V projects with dependable quality and efficiency.
Larry Lapides – Imperas Software Ltd.
The video of this presentation is available on YouTube.