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Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

RISC-V Summit 2022: FutureWatch - RISC-V Models & Tools for Verification, Software Development and Architectural Exploration

RISC-V Summit 2022 FutureWatch talk

The design freedoms of RISC-V offer systems and SoC developers new flexibility to optimize a processor for the requirements of the target application. Now Architectural Exploration is not just about the configuration of multi-core designs, but the analysis of the application and potential advantages of custom instructions. Custom extension can boost the performance for a target class of operations, or support new multi-core communication methods.
Software development with virtual prototypes is well established, but new to RISC-V is the advantage of these platforms offer to end users migrating legacy applications to the new RISC-V based device, well before silicon is available.
For SoC teams optimizing a RISC-V processor they also need to address the additional challenge of RISC-V verification, open standards such as RVVI (RISC-V Verification Interface) are helping the ecosystem support for standards-based test benches and Verification IP.

This talk highlights the RISC-V models that are unifying the hardware, software, and verification teams across all phases of RISC-V projects with dependable quality and efficiency.


Presenter:
Larry Lapides – Imperas Software Ltd.


The video of this presentation is available on YouTube.

View Document

Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

ARM TrustZone Platform Modeling Application Note

NSITEXE’s RISC-V Success Using ImperasDV and Cadence

Using OVP Fast Processor Models with OVPsim and other simulators

Comments

  • Shoi Egawa

    CEO of SELTECH Corporation

    Imperas enables SELTECH to create new value for our customers by reducing time and cost-to-market, while improving their overall system performance. Our work with market leaders including Imperas and Imagination will help us continue to strengthen our position across the Japanese electronics market and beyond.

  • Dr. Charlie Su, CTO and EVP

    Andes Technology

    All Andes RISC-V CPU cores are extensible. ACE empowers SoC designers to easily add custom instructions on top of our highly efficient cores to fulfill domain-specific acceleration and bring their SoC performance to the next level.

    Our RISC-V CPU cores are supported by the Imperas simulators already. We are excited to extend our cooperation to enable ACE users to use the Imperas fast simulators so that software engineers can also be engaged with the full development cycle and from the early stage.