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DVCon 2020 Paper on Rolling the Dice with Random Instructions is the Safe Bet on RISC-V Verification


The traditional SoC verification approach has until now been based on the fundamental assumption of known good processor IP from the mainstream semiconductor IP providers. With Open ISA’s such as RISC-V, developers can exploit a greater degree of implementation flexibility but must also assume a greater role in the verification task. To complement established techniques this paper illustrates the approach using an open-source random instruction generator for RISC-V with a cloud-based environment for capacity flexibility to compare implementation RTL against a reference simulation model. This latest framework covers the needs of specialist core designers and all SoC adopters.

Co-Author:       Simon Davidmann - Imperas Software Ltd.
Co-Author:       Lee Moore - Imperas Software Ltd.
Co-Author:       Richard Ho - Google LLC.
Co-Author:       Tao Liu - Google LLC.
Co-Author:       Doug Letcher - Metrics Technologies Inc.
Co-Author:       Aimee Sutton - Metrics Technologies Inc.