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Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

ISA optimizations for hardware and software harmony: Custom instructions and RISC-V extensions

The art of ISA design is the fine balance between gaining performance advantages and enhanced usability

Design & Reuse

The topic of RISC-V custom instructions is growing in importance. This article explains why this subject is becoming so significant, and outlines some of the previous approaches to processor hardware and software optimization to illustrate the techniques that are now possible with RISC-V.
RISC-V is an open ISA (Instruction Set Architecture) that defines the boundary between hardware of the processor design and the software that it will execute, such as operating systems and application programs. In traditional or closed source ISAs the structure and future roadmap is tightly controlled and guided in a particular direction…

To read the full article, click here.


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Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

ARM TrustZone Platform Modeling Application Note

Using OVP Fast Processor Models with OVPsim and other simulators

NSITEXE’s RISC-V Success Using ImperasDV and Cadence

Comments

  • Charlie Hong-Men Su, CTO

    Andes Technology

    Imperas virtual platform solutions and open-source models help accelerate embedded software development, debug and test for our customers. This certification demonstrates our great confidence in the accuracy and value of Imperas support for V5 AndesCore N25 and NX25 processors reference models and simulators for use by our customers, partners, and ecosystem

  • Dr. Luca Benini, chair of digital circuits and systems and one of the originators of the RISC-V PULP project

    ETH Zurich

    RISC-V has made the successful transition from an academic project to achieve commercial adoption. We see a universal need for quality and design assurance that can be supported by riscvOVPsim across all projects as PULP RI5CY cores are increasingly implemented in commercial SoC development.