RISC-V Summit 2022 Expo talk
As RISC-V processors start to be used more and more in SoCs, industry needs to look beyond the RISC-V ISA to the requirements for use. These include a well-verified implementation, the ability to develop, debug and test software, especially early in the project, and the need to explore different implementations, including different processors, multi-hart processors and custom instructions. One common element to these requirements is a high-quality model of the RISC-V cores being used. This presentation will report on the test-driven development methodology used to build the Open Virtual Platforms (OVP) models of RISC-V cores (~100 different cores available in the OVP Library and provided to processor IP developers), and show how these models have been used for design verification, software development and architectural exploration.
Specifically, this presentation discusses how the availability of high-quality models of RISC-V processors impacts the design process, including in design verification (DV), software development and architecture exploration. This talk will show examples of industry uses of these models for those use cases, including step-and-compare DV flows, software and operating system porting and bring up, and analysis and optimization of custom instructions.
Larry Lapides, Imperas Software Ltd.
The video of this presentation is available on YouTube.