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Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

RISC-V Summit 2022: RISC-V Models for Verification, Software Development and Architectural Exploration

RISC-V Summit 2022 Expo talk

As RISC-V processors start to be used more and more in SoCs, industry needs to look beyond the RISC-V ISA to the requirements for use. These include a well-verified implementation, the ability to develop, debug and test software, especially early in the project, and the need to explore different implementations, including different processors, multi-hart processors and custom instructions. One common element to these requirements is a high-quality model of the RISC-V cores being used. This presentation will report on the test-driven development methodology used to build the Open Virtual Platforms (OVP) models of RISC-V cores (~100 different cores available in the OVP Library and provided to processor IP developers), and show how these models have been used for design verification, software development and architectural exploration. 

Specifically, this presentation discusses how the availability of high-quality models of RISC-V processors impacts the design process, including in design verification (DV), software development and architecture exploration. This talk will show examples of industry uses of these models for those use cases, including step-and-compare DV flows, software and operating system porting and bring up, and analysis and optimization of custom instructions.


Presenter:
Larry Lapides, Imperas Software Ltd.
 

The video of this presentation is available on YouTube.

View Document

Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

Using OVP Fast Processor Models with OVPsim and other simulators

Using OVP Fast Processor Models with OVPsim and other simulators

NSITEXE’s RISC-V Success Using ImperasDV and Cadence

Comments

  • Hirohiko Ono, Senior Manager of the MCU Tools Marketing Department

    Renesas Electronics Corporation

    Imperas with its OVP Fast Processor Models is addressing key issues in software development for embedded systems. We are happy to work with Imperas to ensure that high quality models are easily available to our worldwide customers, helping them to develop and test software faster and more easily using virtual platforms.

  • Nobuyuki Ueyama, President

    eSOL TRINITY

    Virtual platforms enable the essential early development of software well before RTL or silicon prototypes are available, which dramatically accelerates the time to market.

    In addition, for the next generation of automotive AI designs, the early architectural exploration of the SoC helps validate the system design and becomes the reference model for RTL verification.