As if Intel testing the RISC-V waters wasn’t news in itself, the semiconductor behemoth’s Intel Pathfinder for RISC-V initiative is now making the headlines. RISC-V is an open standard instruction set architecture (ISA) that offers chip developers the freedom to configure a custom processor with standard extensions and configuration options.
Vijay Krishnan, general manager of RISC-V Ventures at Intel, acknowledges that the adoption of RISC-V is at an inflection point across…

Aspiring to become a facilitator in the open [standard] RISC-V community, Intel is decidedly humble in its approach to enabling SoC designers who use RISC-V cores.

For the world’s largest CPU vendor to become a genuine facilitator for the open [standard] RISC-V community, Intel must demonstrate its intent and commitment. Is its Pathfinder initiative for RISC-V enough? Can Intel gain the trust from those in the RISC-V…

No more not-invented here for the chip giant when it comes to processor architectures.

Much like IBM after the PC architecture ran away from it and almost collapsed Big Blue’s highly profitable minicomputer and mainframe businesses, Intel has been through some soul-searching in the wake of Arm’s expansion from the world of cellular phones into just about everything else. 
Intel has moved from a company that sued relentlessly to try to maintain…

New Integrated Development Environment for RISC-V includes Imperas simulator and reference model as a fixed platform kit for software development and architectural analysis

Oxford, United Kingdom – August 30th, 2022 – Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced a strategic alliance with Intel®…

The functional verification task keeps growing. How well is the industry responding to growing and changing demands?

Semiconductor Engineering sat down to discuss how well verification tools and methodologies have been keeping up with demand, with Larry Lapides, vice president of sales for Imperas Software; Mike Thompson, director of engineering for the verification task group at OpenHW…

The September 8 learning event from Electronic Design will feature in-depth coverage of RISC-V architecture, hardware, software, and a robust panel discussion.

The open [standard] RISC-V instruction set architecture (ISA) has taken the development community by storm as more companies have implemented chips based on RISC-V. The architecture is…

Complete source file access allows easy adoption and enables user extensions for advanced microarchitecture verification that helps all RISC-V projects accelerate time-to-market goals

Oxford, United Kingdom – August 2nd, 2022 – Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced the release of the first open-source…

A fundamental shift in the economics of processing and new use cases are making ASICs cool again.

Semiconductor Engineering sat down to discuss bespoke silicon and what’s driving that customization with Kam Kittrell, vice president of product management in the Digital & Signoff group at Cadence; Rupert Baines, chief marketing officer at Codasip; Kevin McDermott, vice president of marketing at Imperas…

New packaging technology is spawning new markets for IP, but it is not clear how many interface standards will be created and need to be supported.

The design IP market has long been known for constant change and evolution, but the industry trend toward heterogenous integration and chiplets is creating some new challenges and opportunities. Companies wanting to stake out a claim in this area have to be nimble…