Embedded Software Development with Virtual Platforms
Shifting Left with Imperas
No one builds a chip without simulation, right? In this week’s Fish Fry, Amelia Dalton of Electronic Engineering Journal takes a closer look at the value of virtual prototypes to simulate embedded software. Simon Davidmann (CEO - Imperas) and Amelia chat about about why Simon thinks no one should design embedded software without simulation, and the benefits of using virtual platforms to develop a verification and test environment.
In November 2016, Simon Davidmann of Imperas gave a talk on how Imperas technology is being used for Timing Analysis, Power Analysis and Fault Simulation
to assist with Software Verification. Here are the slides. The talk was split into two sections.
The first section covers software verification for embedded systems and provides an overview of the challenges of many processors
in current embedded systems. It leads into the requirements for software verification and introduces specific embedded software development issues. It then
explains using simulation / virtual platforms and advanced tools to make embedded software development easier, quicker, and more affordable.
There are explanations of how simulation can…
The impact of the chip’s changing role in the system is becoming clearer.
Ann Steffora Mutschler of Semiconductor Engineering has written an interesting article on System Level design and its automation.
There are comments from Wally Rhines (chairman & CEO of Mentor), Simon Davidmann (president & CEO Imperas), Nandan Nayampally (VP marketing ARM), Nimish Modi (snr VP Cadence) and John Koeter (VP Synopsys).
Change is underway in the chip design world, creating opportunities and challenges that reach far beyond questions about whether Moore’s Law is slowing or stopping.
Never before in the history of semiconductors has design been so complex and sophisticated, and never has it touched so many lives in so many interesting ways. This is...…
Brian Bailey of Semiconductor Engineering recently chaired a panel at DVCon on ESL.
Expecting the future to replicate the past always leads to surprises and when it comes to migration of abstraction for semiconductor design, the future remains unclear.
Brian interviewed several industry leaders with experience in the field and provides interesting insights into why ESL took a long time to get where it has...
Simon Davidmann, CEO of Imperas was quoted several times. For example Simon said: “Everyone is trying to do more with RTL, more design, more verification, more complexity, and they needed a better solution. The industry came up with a C++ class language (SystemC) and then tried to look at what they could do with it. What is needed is to move…
At the recent DVCon 2016 conference in Silicon Valley, there was a lively and popular panel, with 135 attending despite the early hour. Moderated by Brian Bailey of Semiconductor Engineering, it featured a variety of views on the role of ESL (“Electronic System Level”) in design and verification for both hardware and software.
Panelists included (from left to right below)
Patrick Sheridan, Synopsys
Raik Brinkmann, One Spin
Simon Davidmann, Imperas Software Ltd.
Bryan Bowyer, Mentor
Dave Pursley, Cadence
Adnan Hamid, Breker
Simon Davidmann of Imperas…
EDAC must become an industry organization that looks after all of the companies within the circle of technologies involved in electronic product design
Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at www.aycinena.com. She can be reached at peggy at aycinena dot com. In October Peggy interviewed Simon on his views for an article on EDACafe.
Simon Davidmann, Imperas CEO, has been thinking about the EDA industry for a while, and the consortium that represents it. And like a lot of observers, he thinks change is in the air. In previous blogs, I myself have predicted that EDAC will evolve to offer better representation to IP providers, but Davidmann believes changes…