Imperas and Metrics joining CHIPS Alliance to help drive the verification of RISC-V Open ISA implementations

SAN FRANCISCO – June 18, 2019 – CHIPS Alliance, the leading consortium advancing common, open hardware for interfaces, processors and systems, today announced Imperas and Metrics are joining the organization and the Verification Working Group. Imperas is an independent provider of processor simulation technology and tools for virtual platforms and analysis tools for multicore SoC…

Zurich – Over the last year or so, we’ve heard many times that ‘this is the moment for RISC-V’. So, this week, I attended the RISC-V workshop in Zurich to get an idea of where it really is at right now. The conclusion: while there is still a lot of background work to be done for RISC-V to go mainstream, the signs are that all the triggers to make it happen are now gradually being released.

The biggest challenge is that RISC-V is still perceived as a hobbyist architecture, and this makes it difficult for mainstream companies to adopt, unless it has deep…

OTTAWA, Ontario and ZURICH, June 6, 2019 – The OpenHW Group, a new not-for-profit global organization aims to boost the adoption of open-source processors by providing a platform for collaboration, creating a focal point for ecosystem development, and offering open-source IP for processor cores.iew photos

Headed by Founder and CEO, Rick O'Connor, the OpenHW Group has already recruited 13 sponsor organizations and expects this to grow to 25 by the end of 2019. OpenHW Group is a member of the …

New MIPS Open Partner Offering Helps System-on-Chip (SoC) Developers Run Design Verification in Record Time Using MIPSOpenOVPsim

CAMPBELL, Calif. and OXFORD, England – May 30, 2019 —  Wave Computing® Inc., the Silicon Valley company accelerating artificial intelligence (AI) from the data center to the edge, and Imperas Software Ltd., the leader in virtual platforms and software simulation, introduced a new Instruction Set Simulator (ISS…

At each new process node, gates are free. That opens the door to a lot more IP blocks, and a lot of new challenges.

Driven by each successive generation of semiconductor manufacturing technology, complexity has reached dizzying levels. Every part of the design, verification and manufacturing is more complicated and intense the more transistors are able to be packed onto a die. For these reasons, the entire system must be taken into consideration as a whole…..

To read the article by Ann Mutschler, click…

These eight companies are developing their own RISC-V technologies and are committing to helping third parties do the same to help push adoption of the open-source chip architecture.

RISC-V (pronounced “risk five”), the open-source architecture for chip design, has been making a lot of noise in the past few years. The open source nature of RISC-V promises…

The road to optimized tradeoff automation is long. Changing attributes along the way can make it even more difficult.

Complexity challenges long-held assumptions. In the past, the semiconductor industry thought it understood performance/area tradeoffs, but over time it became clear this is not so simple. Measuring performance is no longer an absolute. Power has many dimensions including peak, average, total energy and heat, and power and function are tied together.

Design teams are now dealing with the implication of safety and security, which have considerable impact on power/…

Highlights of the inaugural Verification 3.0 Innovation Summit in Silicon Valley March 2019.

I’m that rare person, a native (even second generation) Californian, and grew up going to the Southern California beaches during the summers. I earned my Red Cross…

Showing that a processor core adheres to a specification becomes more difficult when the specification is extensible.

The open-standard RISC-V instruction set architecture (ISA) continues to gain momentum, but the flexibility of RISC-V creates a problem—how do you know if a RISC-V implementation fits basic standards and can play well with other implementations so they all can run the…