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Imperas at OpenHW Day, April 1 2021

Imperas participating at the online virtual event highlighting the latest developments for RISC-V Verification for the open source CORE-V processor IP family.

 

RISC-V Week 2021 & OpenHW Day

Imperas Software Ltd., the leader in RISC-V processor verification technology, today announced their participation at the OpenHW Day as part of RISC-V Week 2021. OpenHW Day is an online virtual event featuring presentations and panels on the latest developments on the CORE-V IP Cores, running projects and supporting infrastructure. Imperas will present updates and demos for the RISC-V verification reference model, software simulation, plus join the panel discussions for interactive Q&A with the on-line attendees.

OpenHW Panel:
The panel discussion on OpenHW with key participants based in Europe including Simon Davidmann of Imperas
OpenHW Software Task Group Projects:
The Imperas talk will feature updates on Software Models and ISS (Instruction Set Simulator) for CORE-V
OpenHW CORE-V Verif: 
This talk will also feature a hands-on demo of Imperas RISC-V verification reference model and SystemVerilog test bench and supporting infrastructure

During the live sessions and breaks, Imperas staff will be available for interactive Q&A with attendees throughout the event.

Free! Registration is free for the 2021 RISC-V Week including the OpenHW Day, see more details at https://open-src-soc.org

 

About Imperas

For more information about Imperas, please see www.imperas.com. Follow Imperas on LinkedIn, twitter @ImperasSoftware and YouTube.

All trademarks or registered trademarks are the property of their respective holders.

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Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

Using OVP Fast Processor Models with OVPsim and other simulators

ARM TrustZone Platform Modeling Application Note

NSITEXE’s RISC-V Success Using ImperasDV and Cadence

Comments

  • Charlie Hong-Men Su, CTO

    Andes Technology

    Imperas virtual platform solutions and open-source models help accelerate embedded software development, debug and test for our customers. This certification demonstrates our great confidence in the accuracy and value of Imperas support for V5 AndesCore N25 and NX25 processors reference models and simulators for use by our customers, partners, and ecosystem

  • Hiroyasu Hasegawa, CTO

    hd Lab, Japan

    For our SystemC training courses, we want the attendees to focus on building SystemC models, and how to use those models. By using OVP Fast Processor Models, which work easily in SystemC virtual platforms, students do not have to worry about processor models, and are able to get the most out of our courses. The OVP models work well in our SystemC environment and also with other SystemC tools. We are excited to be able to expand our design service offerings in virtual platforms to our customers.