Imperas participating at the online virtual event highlighting the latest advances for UVM RISC-V Verification with RISC-V Processor Reference Models and SystemVerilog.
Imperas Software Ltd., the leader in RISC-V processor verification technology, today announced their participation at CadenceLIVE Americas 2021, with two technical presentations on the latest advances for RISC-V verification.
‘The Step-and-Compare methodology for high quality RISC-V processor verification’
• When: Schedule TBD
The open standard ISA of RISC-V has generated significant interest around custom processor design options and the associated design freedoms beyond the roadmap of the mainstream processor IP providers. Thus, RISC V has enabled any SoC developer to consider undertaking a custom processor design, which in turn has stimulated the interest in adapting the established SoC design verification (DV) flows based on UVM and SystemVerilog to also address the complexities of processor verification.
This talk introduces the various options for RISC-V processor verification from the simple trace analysis through to the latest techniques with test benches that support UVM SystemVerilog with Step-and-Compare for asynchronous events. With illustration of the various options and approaches including details of bugs found on some popular open-source cores.
‘The open verification method used by OpenHW for the CV32E40P RISC-V core’
• When: Schedule TBD
This talk explores the background, development and implementation of the OpenHW verification environment for CV32E40P known as “core-v-verif”. Since the goal of the project is to support adoption on of an open-source core, the initial deliverable quality is not the only concern. One attractive aspect of an open-source core is the potential for adopters to modify, adapt, or extend the base core features. Thus, the verification plan needs to anticipate the future use case with flexibility built in and clear documentation.
About CadenceLIVE Americas 2021
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