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The RISC-V market is ripe for domain specific designs.

 

Codasip article on Semiconductor Engineering

 

We weren’t sure what to expect from our first major attendance at a #RISCVSummit. Although we were a founding member of RISC-V – as we’ve been saying quite a lot recently – we have been hiding our light under a bushel…

To read the full article by Rupert Baines, published by Semiconductor Engineering…

Cache coherency is expensive and provides little or negative benefit for some tasks. So why is it still used so frequently?

Semiconductor Engineering

 

Cache coherency, a common technique for improving performance in chips, is becoming less useful as general-purpose processors are supplemented with, and sometimes supplanted by, highly specialized accelerators and other processing elements.
While cache coherency won’t disappear anytime…

With its new ImperasDV solution, the company aims at enabling all RISC-V developers to accomplish the complex task of processor IP verification more efficiently.

EDACafe

“The greatest migration in verification responsibility in the history of EDA,” from processor IP vendors to SoC designers: this, according to Imperas Software, is the challenge facing SoC development teams as they take advantage from RISC-V customization capabilities…

Interview with Sanjay Gangal following the announcement of ImperasDV for RISC-V processor verification at the co-located DAC and RISC-V Summit 2021.

EDACafe

The open ISA of RISC-V is generating a lot of interest on the new design freedoms for processor hardware, in this interview Sanjay explores the implications for software development and the growing demand for processor verification solutions. Highlighting the recent announcements on ImperasDV, the latest…

Embedded Computing Design

RISC-V is known as an open-standard instruction set architecture (ISA) whose base instructions have been frozen to minimize complexity. But more recently it has added a wide range of custom extensions and enhancements that are making it increasingly popular amongst SoC designers building application-specific systems.
The custom functionality adopted in these architectures is often enhanced…

The application of old techniques to new problems only gets you so far. To remove limitations in AI processors, new thinking is required.

Semiconductor Engineering

 

Software and hardware both place limits on how fast an application can run, but finding and eliminating the limitations is becoming more important in this age of multicore heterogeneous processing.
The problem is certainly not new. Gene Amdahl (1922-2015) recognized the issue and published a paper about…

With a combined 100 years of experience and 10 years of effort creates new ImperasDV killer-app for RISC-V verification engineers

ImperasDV - Quality Verification for the design freedom of RISC_V

Oxford, United Kingdom – December 6th, 2021 – Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced ImperasDVTM as the integrated solution for RISC-V processor verification. RISC-V is an open standard ISA (Instruction Set…

Imperas RISC-V golden reference models and Verification IP used for functional RISC-V Processor Verification and Architectural Compatibility Testing.

 

MIPS selects Imperas RISC-V processor verification

Oxford, United Kingdom – November 29th, 2021 – Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced with MIPS, Inc., the processor technology company focused on the commercialization of RISC-based processor architectures and IP…

Verification and debug of AI is a multi-level problem with several stakeholders, each with different tools and responsibilities.

Semiconductor Engineering

 

When an AI algorithm is deployed in the field and gives an unexpected result, it’s often not clear whether that result is correct.
So what happened? Was it wrong? And if so, what caused the error? These are often not simple questions to answer. Moreover, as with all verification problems, the only way…