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eeNews Europe

Imperas Software in the UK has extended the RVVI (RISC-V Verification Interface) with virtual peripherals to support asynchronous events and system level interrupts. RVVI is an open specification with a common methodology for the key components of the testbench to connect the RISC-V processor RTL instruction trace and reference models to fully support the lock-step-compare co-simulation.

The RVVI…

The latest posts on the EDA, IP and SoC Industries

 

EDACafe

 

The Design Automation Conference is back to its usual summer timeframe – again at the Moscone Center in San Francisco – with over one hundred exhibitors and a rich conference program that covers a wide range of topics including artificial intelligence, autonomous systems, RISC-V, security, embedded systems and more. Here we will briefly…

EENews Europe

It may come as a surprise that over 10 billion RISC-V processor cores have shipped. After all, it took ARM 17 years to reach that milestone in 2008, and RISC-V could be considered to be in its infancy with a consensus that the eco-system still needs to evolve, particularly around security. These two factors result from the open standard approach to an inherently custom technology. The instruction set can be easily extended to accelerate key instructions, reducing die area and…

With a unified, standards-based approach to verification and Verification IP reusability, mutual customers can seamlessly transition between RISC-V processor and system level DV

Imperas and Breker partnership for processor-to-system level verification for RISC-V

Oxford, United Kingdom – July 7th, 2022 – Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced a partnership with Breker Verification Systems, a leading…

RISC-V Architectural Validation test suites updated for the ratified extensions including Vectors, Crypto (scalar), Bit Manipulation, and the new addition of Embedded (E) extension

Imperas riscvOVPsimPlus Free RISC-V Reference model plus latest test suites

Oxford, United Kingdom – July 6th, 2022 – Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced the latest RISC-V test suites and updates to the free

EE Journal

 

I love computers (but only in a manly-man way, you understand). I’m not talking about the end-products that sit on our desks, hang out in our pockets, or lurk around us as we meander our way through the world, although I’m certainly fond of these little rascals—I’m much more interested in their “brains” in the form of their processing units where all the decision-making and number-crunching takes placel….
 

To read the full EE Journal article by…

Heterogeneous designs and AI/ML processing expose the limitations of existing methodologies and tools.

Semiconductor Engineering

 

Defining what a processor is, and what it is supposed to do, is not always as easy as it sounds. In fact, companies are struggling with the implications of hundreds of heterogenous processing elements crammed into a single chip or package. Companies have extensive verification methodologies, but not for validation. Verification is a…

The RISC-V Pavilion at Embedded World 2022 highlighted a range of advancements, from the first RISC-V–based GPU to a new open-source RISC-V development kit.

Electronic Products

 

Embedded World 2022 was the place to be for the latest RISC-V developments. Innovations ranged from Think Silicon’s first RISC-V–based GPU, targeting 32-bit SoCs, to the OpenHW Group’s new open-source RISC-V development kit, based on the OpenHW CORE-V…

It may not be the most glamorous type of software development, but getting it right is essential for the success of any hardware platform.

Semiconductor Engineering

 

Hardware and software are two sides of the same coin, but they often live in different worlds. In the past, hardware and software rarely were designed together, and many companies and products failed because the total solution was unable to deliver.
The big question is…