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Keynote: Are the RISC-V design freedoms leading to RISK in Verification quality?


RISC-V Summit 2021

Traditional SoC projects estimate that 50-80% of the cost/effort will be for verification, but that is based the traditional approach using mainstream providers with pre-verified processor IP cores. RISC-V offers more options to SoC Developers, from developing a custom core, downloading an open-source project, selecting from one of the new IP providers, plus adding custom instructions to any of these starting points.
The flexibility of RISC-V appears to imply an increase in the DV scope of work for any SoC project with a customized RISC-V core, in this talk we will introduce the Imperas Reference Model based solutions for RISC-V processor verification.

Speaker:     Larry Lapides – Imperas Software 

The PDF of the slides used in this talk are available at this link

This RISC-V Summit 2021 presentation can be viewed on the RISC-V YouTube channel here.