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Revolutionizing Embedded Software Development

RISC-V Summit 2021 - DV Keynote talk: Are the RISC-V design freedoms leading to RISK in Verification quality?

Abstract:

Traditional SoC projects estimate that 50-80% of the cost/effort will be for verification, but that is based the traditional approach using mainstream providers with pre-verified processor IP cores. RISC-V offers more options to SoC Developers, from developing a custom core, downloading an open-source project, selecting from one of the new IP providers, plus adding custom instructions to any of these starting points.
The flexibility of RISC-V appears to imply an increase in the DV scope of work for any SoC project with a customized RISC-V core, in this talk we will introduce the Imperas Reference Model based solutions for RISC-V processor verification.

Co-Author:       Larry Lapides – Imperas Software
Co-Author:       Lee Moore – Imperas Software

The video of this presentation is available at this link.
 

 

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Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

ARM TrustZone Platform Modeling Application Note

Using OVP Fast Processor Models with OVPsim and other simulators

NSITEXE’s RISC-V Success Using ImperasDV and Cadence

Comments

  • Nobuyuki Ueyama, President

    eSOL TRINITY

    Virtual platforms enable the essential early development of software well before RTL or silicon prototypes are available, which dramatically accelerates the time to market.

    In addition, for the next generation of automotive AI designs, the early architectural exploration of the SoC helps validate the system design and becomes the reference model for RTL verification.

  • Yunsup Lee, co-founder and CTO

    SiFive

    SiFive’s Core Designer allows our customers to customize our broad portfolio of RISC-V Core IP for their particular application. The donation of a robust, commercial-quality simulator such as riscvOVPsim™ will enable them to adopt RISC-V even faster. This is the level of close industry collaboration that will drive the successful adoption of RISC-V.