Imperas Software in the UK has extended the RVVI (RISC-V Verification Interface) with virtual peripherals to support asynchronous events and system level interrupts. RVVI is an open specification with a common methodology for the key components of the testbench to connect the RISC-V processor RTL instruction trace and reference models to fully support the lock-step-compare co-simulation.
The RVVI flexibility supports the full range of RISC-V specifications and features that can be adopted with increasing levels of complexity for designs with privilege modes, vector extensions, out-of-order pipelines, multi-threading, multi-hart, plus user-defined custom instructions and extensions. RVVI supports the innovation of RISC-V with the flexibility required for verification IP and reuse as DV teams scale up to support the rapid growth in RISC-V verification projects…
To read the full eeNews Europe article by Nick Flaherty, click here.