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OpenHW open source CORE-V processor IP: a RISC-V story that leads with verification

OpenHW Processor DV Flow with Imperas RISC-V Golden Reference Model


The open specification of the RISC-V ISA (Instruction Set Architecture) permits a range of possibilities for processor implementation with a modular approach for standard and custom extensions. In addition, implementations may be shared commercially or as open source, and adopters beyond the original design team can use these directly or as a basis for further modifications and enhancements.
The OpenHW Group is a not-for-profit, global organization of members based on the principles of open source hardware IP, with full commercial grade standards for delivery and quality …

To read the full article published by RISC-V International, click here.