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Imperas is now a part of Synopsys

Imperas at IP SoC Silicon Valley, April 26-27 2022

Imperas is participating at the Design & Reuse IP-SoC event with a RISC-V keynote on the state of the ecosystem support and highlighting the use of RISC-V Reference Models for Verification, Software Development and Architectural Exploration.

IP-SoC Silicon Valley 2022

Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced their participation at the D&R IP-SoC Silicon Valley 202, including a RISC-V keynote, technical presentation, plus in-person demonstrations and discussions on the latest advances for RISC-V verification. 

 

Keynote: ‘The RISC-V Ecosystem: Fragmentation or Convergence?’
•    Speaker:     Larry Lapides – Imperas Software
•    When:         April 26, 2022 – 11:40am (Mountain View, California)

Abstract: RISC-V offers SoC developers the opportunity to uniquely optimize a custom processor, configured ‘just right’ for the target application. IP providers have flourished with the open standard ISA, with many commercial, open source and custom options for the SoC developers to select from. The design side is clear blue sky and the greenest of green fields. 
Previous processor ecosystems have been based on solving common problems, leveraging reuse and offering a consistency of experience across closely related hardware implementations.  RISC-V is breaking all the rules.  The open instruction set architecture (ISA) standard is evolving and adapting rapidly, and almost all of the currently available IP cores and devices are very different.  Is this to the point that the RISC-V community is on the brink of fragmentation and chaos?  Or with the recent ratification of new portions of the RISC-V ISA, and the acceleration of adoption, will the RISC-V ecosystem see convergence, leverage, cooperation? 
This presentation reviews the current state of the RISC-V ecosystem, noting successes as well as areas needing improvement, and attempts to provide attendees with information to answer the question: Can the ecosystem accommodate the unique flexibility and design opportunity of RISC-V with the efficiency that is normally associated with mass adoption? 

 

Presentation: ‘RISC-V Models for Verification, Software Development and Architectural Exploration’
•    Speaker:       Larry Lapides – Imperas Software
•    Co-author:   Lee Moore – Imperas Software
•    When:           April 27, 2022 – 2:40pm (Mountain View, California)

Abstract: As RISC-V processors start to be used more and more in SoCs, industry needs to look beyond the RISC-V ISA to the requirements for use.  These include a well-verified implementation, the ability to develop, debug and test software, especially early in the project, and the need to explore different implementations, including different processors, multi-hart processors and custom instructions.  One common element to these requirements is a high-quality model of the RISC-V cores being used.  This presentation will report on the test-driven development methodology used to build the Open Virtual Platforms (OVP) models of RISC-V cores (~100 different cores available in the OVP Library and provided to processor IP developers), and show how these models have been used for design verification, software development and architectural exploration. 
Specifically, this presentation will discuss how the availability of high-quality models of RISC-V processors impacts the design process, including in design verification (DV), software development and architecture exploration.  This talk will show examples of industry uses of these models for those use cases, including step-and-compare DV flows, software and operating system porting and bring up, and analysis and optimization of custom instructions.  


For more information, or to request meeting or 1-1 demo with Imperas staff during IP SoC Silicon Valley 2022 please contact info@imperas.com.

 

About D&R IP-SoC Silicon Valley 2022
Design & Reuse IP-SoC Silicon Valley 2022 will be held at the Computer History Museum, 1401 N. Shoreline Blvd, Mountain View, CA 94043, USA on April 26-27 2022. For registration and more information, click here.

 

 

About Imperas

For more information about Imperas, please see www.imperas.com. Follow Imperas on LinkedIn, twitter @ImperasSoftware and YouTube.

All trademarks or registered trademarks are the property of their respective holders.

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Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

Using OVP Fast Processor Models with OVPsim and other simulators

RISC-V Processor Verification: ImperasDV with Synopsys VCS and Verdi Application Note

RISC-V Custom Instruction Flow Application Note

Comments

  • Dr. Luca Benini, chair of digital circuits and systems and one of the originators of the RISC-V PULP project

    ETH Zurich

    RISC-V has made the successful transition from an academic project to achieve commercial adoption. We see a universal need for quality and design assurance that can be supported by riscvOVPsim across all projects as PULP RI5CY cores are increasingly implemented in commercial SoC development.

  • Rick O’Connor, President & CEO

    OpenHW Group

    Fundamental to the OpenHW CORE-V open-source processor family is high-quality verification that has been achieved with the help and support of the dedicated OpenHW members and contributors.

    I am excited that Simon [Davidmann, CEO of Imperas] is lending his verification expertise and vision [as Chair] to expand the scope of the OpenHW Verification Task Group to address industry-wide standards and methodologies for all RISC-V adopters.