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Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

Imperas to present at Andes RISC-V Con Taiwan - May 16, 2023

Imperas highlights include Andes-based RISC-V virtual platforms for software driven design optimizations with Imperas processor reference models and analysis tools with Andes ACE.

Andes Technology

Imperas Software Ltd., the leader in RISC-V models and simulation solutions, today announced their participation at Andes RISC-V Con 2023 in Hsinchu, Taiwan.

 

Presentation:
Develop AI and Automotive platforms leveraging use of Virtual Platforms

Abstract: This talk outlines the software driven approach for architectural exploration to optimize Andes ACE extensions for your applications using the Imperas reference models and analysis tools. Plus, the key advantage of Fixed-Platform-Kits with the key go-to-market support for end users.


Speaker: Katherine (Kat) Hsu, Imperas Software Ltd

 

For more information, or to set up meetings with Imperas at Andes DevCon, please email info@imperas.com

 

Andes RISC-V Con Hsinchu, Taiwan
When:         Tuesday May 16th, 2023
Where:        In person plus virtual attendance options, Hsinchu, Taiwan

This event is free to attend but registration is required, please visit Andes RISC-V Con to register.


 

 

About Imperas

For more information about Imperas, please see www.imperas.com. Follow Imperas on LinkedIn, twitter @ImperasSoftware and YouTube.

All trademarks or registered trademarks are the property of their respective holders.

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Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

NSITEXE’s RISC-V Success Using ImperasDV and Cadence

RISC-V Custom Instruction Flow Application Note

NSITEXE’s RISC-V Success Using ImperasDV and Cadence

Comments

  • Charlie Hong-Men Su, CTO and Senior VP

    Andes Technology

    The Imperas virtual platform solutions for software development, debug and test, along with their open-source models, comprise an excellent methodology for development of embedded software for SoCs based on V5 AndesCore N25 and NX25 RISC-V processors.

  • Dr. Luca Benini, chair of digital circuits and systems and one of the originators of the RISC-V PULP project

    ETH Zurich

    RISC-V has made the successful transition from an academic project to achieve commercial adoption. We see a universal need for quality and design assurance that can be supported by riscvOVPsim across all projects as PULP RI5CY cores are increasingly implemented in commercial SoC development.