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Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

Multicore Debug Evolves To The System-Level

Complexity is making this process more difficult, but new and better approaches are being developed.

Semiconductor Engineering

 

The proliferation and expansion of multicore architectures is making debug much more difficult and time-consuming, which in turn is increasing demand for more comprehensive system-level tools and approaches.
Multicore/multiprocessor designs are the most complex devices to debug. More interactions and interdependencies between cores mean more things possibly can go wrong. In fact, so many problems are possible that engineering teams frequently wonder where to begin. Compared with single-core, multiple-core designs include more execution streams to debug at the same time. In addition, instructions are executed in each thread, and complex interactions occur between each core…

 

To read the full Semiconductor Engineering article by Ann Steffora Mutschler, click here.


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Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

RISC-V Processor Verification: ImperasDV with Synopsys VCS and Verdi Application Note

ARM TrustZone Platform Modeling Application Note

ARM TrustZone Platform Modeling Application Note

Comments

  • Hugh O’Keeffe, CEO

    Ashling

    We are excited to offer our customers target debug support for the Imperas golden reference models of the MIPS eVocore P8700 Multiprocessor.

    This collaboration between Ashling, MIPS, and Imperas enables developers to accelerate their RISC-V software development, testing, and debugging, ultimately leading to faster time-to-market for next-generation domain-specific devices.

  • Hideki Sugimoto, CTO

    NSITEXE, Inc., a group company of DENSO Corporation.

    The NSITEXE Akaria processors, developed with the use of Imperas RISC-V verification technology, are targeted to address the high-performance requirements for AI and automotive requirements with the necessary features and quality to achieve the ISO 26262 ASIL D functional safety standard, in addition to optimized and efficient processors for the next generation embedded applications.

    As the NSITEXE Akaria processors are adopted across a wide range of next generation of automotive, safety critical, and embedded applications, the partnership with Imperas now also provides the dependable reference models that support developers across the entire design and development phase of an SoC project.