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Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

Imperas to present at Andes RISC-V Con Silicon Valley - June 27, 2023

Imperas highlights include Andes-based RISC-V virtual platforms for software driven design optimizations with Imperas processor reference models and analysis tools with Andes ACE.

Andes Technology

Imperas Software Ltd., the leader in RISC-V models and simulation solutions, today announced their participation at Andes RISC-V Con 2023 in San Jose, California.

Presentation:
Virtual platform use in early artificial intelligence software exploration influences SoC architectures

Abstract: This talk outlines the software driven approach for architectural exploration to optimize Andes ACE extensions for your applications using the Imperas reference models and analysis tools. Plus, the key advantage of Fixed-Platform-Kits with the key go-to-market support for end users.

Speaker: Katherine (Kat) Hsu, Imperas Software Ltd


For more information, or to set up meetings with Imperas at Andes RISC-V Con, please email info@imperas.com

 

Andes RISC-V Con Silicon Valley, California
When:      1:30am-5pm Tuesday June 27th, 2023
Where:     DoubleTree by Hilton Hotel San Jose, 2050 Gateway Place San Jose, CA 95110

This event is free to attend but registration is required, please visit Andes RISC-V Con to register.
 

 

 

About Imperas

For more information about Imperas, please see www.imperas.com. Follow Imperas on LinkedIn, twitter @ImperasSoftware and YouTube.

All trademarks or registered trademarks are the property of their respective holders.

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Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

NSITEXE’s RISC-V Success Using ImperasDV and Cadence

RISC-V Processor Verification: ImperasDV with Synopsys VCS and Verdi Application Note

ARM TrustZone Platform Modeling Application Note

Comments

  • Karel Masarik, CEO and Co-Founder

    Codasip Ltd

    As RISC-V adoption grows throughout the industry in a variety of application areas, so does the need for robust simulation support from both commercial and open source suppliers. We welcome Imperas' contributions to the rapidly accelerating RISC-V ecosystem.

  • Dr. Charlie Su, President and CTO

    Andes Technology Corp.

    RISC-V represents the potential for innovation, and it is the implementation of great ideas that are really generating exceptional results.

    To unlock such potentials, Andes provides the AndeSysC™ environment, an extensible and near-cycle accurate SystemC model library for all AndesCore®. SoC architects can use it to construct a SystemC based virtual platform for performance evaluation of critical code segment and hardware/software co-optimization. ACE technology helps users implement custom functions and instructions, and it directly connects to the AndeSysC™ environment. Now with the close integration with the Imperas fast reference models and tools, design teams can embark on architecture exploration with complete application software for the next generation of domain specific devices with a seamless path to ACE implementation.