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Verification of RISC-V Open ISA processors using Imperas

Imperas presentation on "Verification of RISC-V Open ISA processors: New Freedoms in Design Require New and Improved Verification Methodologies" by Lee Moore and Simon Davidmann, of Imperas, at the RISC-V pavilion during the virtual event for DAC 2020.

The RISC-V community using Open Source and/or commercial cores need to consider the test plans for a many-core SoC based on Open ISA processors, all of which may be different in any number of ways - from implementations with micro-architectural distinctions, to optional features and optimized custom instructions.

A test plan requires 4 things - a design to test, a DV plan, some tests to run and a reference to compare against. Compliance is the essential baseline test for an Open ISA implementation, but coverage frameworks and methods help define the quality metrics of progress within the complete processor DV plan. Random instruction testing offers the potential to explore the design state in challenging and unexpected ways, the art of the test comes from focused attention across corner case scenarios. This talk covers the latest updates and methods for coverage analysis and reference model-based verification.


This DAC presentation can be viewed on the YouTube channel for DAC TV here.