x

Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

NSITEXE Inc. Denso: Vector Compliance Testing for RISC-V - Hideki Sugimoto and Koji Adachi

NSITEXE presentation on "Vector Compliance Testing for RISC-V" by NSITEXE Inc. (Denso subsidiary) by Hideki Sugimoto - CTO, and Koji Adachi - CPU Architect, with guest speaker Simon Davidmann, CEO at Imperas, at the RISC-V Global Forum during the virtual event on September 3 2020.

The first step to testing a RISC-V vector instruction implementation is to test compliance to the specification. To do this requires both compliance tests and a reference model. NSITEXE, with its Data Flow Processor (DFP) IP block, required such testing for its implementation of the vector engine. The Imperas RISC-V ISS, riscvOVPsim, is in use as the reference model for the Imperas RISC-V Vector Compliance Test Suite (CTS). Imperas has developed a Directed Compliance Test Generator, which achieves over 95% functional instruction coverage with those tests generated. Using the Vector CTS for the NSITEXE configuration has enabled confirmation of compliance with v0.8 of the RISC-V vector specification.

This paper discusses the NSITEXE DFP vector engine implementation, the generation of the Vector Compliance Tests for the NSITEXE configuration and the results of those tests including coverage data.

 

This RISC-V Global Forum presentation can be viewed on the YouTube channel for RISC-V here.

 

 

 

Comments

  • Jim Nicholas

    VP, MIPS Business Operations, Imagination Technologies

    It is exciting and gratifying to see members of the MIPS ecosystem working together to provide new software, tools and methodology to MIPS users. The hardware virtualization features in our MIPS M51xx CPUs make them a unique and powerful offering for next-generation microcontroller-class products. We’re pleased to see these new solutions from Imperas and SELTECH that can help our customers more quickly and easily bring secure, reliable devices to market.

  • Nobuyuki Ueyama, President

    eSOL TRINITY Co., Ltd.

    RISC-V is enabling a new wave of design innovation, and successful projects depend on quality processor IP and dependable design platforms that offer architecture exploration and early software development.

    Having supported the NSITEXE team on the extensive internal RISC-V processor verification, as well as on the virtual platform development task for multiple projects, the support team at eSOL TRINITY is now able to assist developers as they build the next generation of SoC designs using the Imperas tools and reference models for the NSITEXE Akaria processors.