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Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

Introduction to RISC-V processor verification methodology with dynamic testbench for asynchronous events

 

SemIsrael Tech Webinar, February 22 2022

Abstract:
For SoC designers adopting RISC-V, tackling the processor DV tasks presents some new challenges. The established SoC flows have some standard assumptions – test benches written for UVM SystemVerilog flows and known good processor IP from a mainstream supplier. The availability of open-source RISC-V cores and the growing interest to add custom extensions are all increasing the DV tasks.
The basic RISC-V compliance suite is insufficient to achieve the coverage requirements for a complete DV test plan, and comparison-based testing with predicted results has built-in limitations. The latest work on dynamic test benches allows the processor RTL to be subjected to the full range of asynchronous events and debug operations. Interactive dynamic test benches allow both detection of issues and also efficient investigation for a timely resolution. This talk will present the latest results from extensively testing some popular open-source cores, including discussion of a new open standard for test bench interfaces.

Speaker:     Larry Lapides – Imperas Software

The PDF of the slides used in this talk are available at this link

This presentation can be viewed YouTube.

Comments

  • Hugh O’Keeffe, CEO

    Ashling

    We are excited to offer our customers target debug support for the Imperas golden reference models of the MIPS eVocore P8700 Multiprocessor.

    This collaboration between Ashling, MIPS, and Imperas enables developers to accelerate their RISC-V software development, testing, and debugging, ultimately leading to faster time-to-market for next-generation domain-specific devices.

  • Yunsup Lee, co-founder and CTO

    SiFive

    SiFive’s Core Designer allows our customers to customize our broad portfolio of RISC-V Core IP for their particular application. The donation of a robust, commercial-quality simulator such as riscvOVPsim™ will enable them to adopt RISC-V even faster. This is the level of close industry collaboration that will drive the successful adoption of RISC-V.