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Introduction to RISC-V processor verification methodology with dynamic testbench for asynchronous events


SemIsrael Tech Webinar, February 22 2022

For SoC designers adopting RISC-V, tackling the processor DV tasks presents some new challenges. The established SoC flows have some standard assumptions – test benches written for UVM SystemVerilog flows and known good processor IP from a mainstream supplier. The availability of open-source RISC-V cores and the growing interest to add custom extensions are all increasing the DV tasks.
The basic RISC-V compliance suite is insufficient to achieve the coverage requirements for a complete DV test plan, and comparison-based testing with predicted results has built-in limitations. The latest work on dynamic test benches allows the processor RTL to be subjected to the full range of asynchronous events and debug operations. Interactive dynamic test benches allow both detection of issues and also efficient investigation for a timely resolution. This talk will present the latest results from extensively testing some popular open-source cores, including discussion of a new open standard for test bench interfaces.

Speaker:     Larry Lapides – Imperas Software

The PDF of the slides used in this talk are available at this link

This presentation can be viewed YouTube.