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Imperas Paper at Embedded World 2015 on Parallel Simulation Accelerates Embedded Software
Development Debug and Test

For any simulation technology, the key factors for usability are performance and controllability/observability.
For instruction accurate virtual platforms, the controllability and observability have been successfully addressed in various ways,
including using APIs for the processor models and tools integrated in the simulation environment. In the area of performance, where near
real time simulation performance is required, virtual platforms have been limited to single thread execution because of the need for
determinism in the simulation. This need is driven by the loss of many of the key benefits of controllability and observability if the
simulation is not repeatable. While multiple threads on multiple cores of the host x86 PC offer the hope of performance improvement, the
overhead for synchronizing multiple simulation execution threads to maintain deterministic simulation results has cancelled out any
performance gains realized by parallelizing the simulation.

A new synchronization algorithm has been realized, with much lower overhead, so that significant performance gains have been achieved.
Performance gains of over 2x have been achieved for symmetric multiprocessor (SMP) systems simulating on a 4-core host machine, while
performance gains of over 3x have been achieved for asymmetric multiprocessor (AMP) systems. The same principals have also been applied
to accelerating the performance of virtual platforms where the performance bottleneck is one or more of the models used for accelerating
specific applications such as image recognition.